An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background- calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time DT of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output ◦range [0.42 - 2.52] V, over the temperature range [-20 , 85] C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Doctor of Philosophy

dissertationOptics is an old topic in physical science and engineering. Historically, bulky materials and components were dominantly used to manipulate light. A new hope arrived when Maxwell unveiled the essence of electromagnetic waves in a micro perspective. On the other side, our world recently embraced a revolutionary technology, metasurface, which modifies the properties of matter-interfaces in subwavelength scale. To complete this story, diffractive optic fills right in the gap. It enables ultrathin flat devices without invoking the concept of nanostructured metasurfaces when only scalar diffraction comes into play. This dissertation contributes to developing a new type of digital diffractive optic, called a polychromat. It consists of uniform pixels and multilevel profile in micrometer scale. Essentially, it modulates the phase of a wavefront to generate certain spatial and spectral responses. Firstly, a complete numerical model based on scalar diffraction theory was developed. In order to functionalize the optic, a nonlinear algorithm was then successfully implemented to optimize its topography. The optic can be patterned in transparent dielectric thin film by single-step grayscale lithography and it is replicable for mass production. The microstructures are 3?m wide and no more than 3?m thick, thus do not require slow and expensive nanopatterning techniques, as opposed to metasurfaces. Polychromat is also less demanding in terms of fabrication and scalability. The next theme is focused on demonstrating unprecedented performances of the diffractive optic when applied to address critical issues in modern society. Photovoltaic efficiency can be significantly enhanced using this optic to split and concentrate the solar spectrum. Focusing through a lens is no news, but we transformed our optic into a flat lens that corrects broadband chromatic aberrations. It can also serve as a phase mask for microlithography on oblique and multiplane surfaces. By introducing the powerful tool of computation, we devised two imaging prototypes, replacing the conventional Bayer filter with the diffractive optic. One system increases light sensitivity by 3 times compared to commercial color sensors. The other one renders the monochrome sensor a new function of high-resolution multispectral video-imaging

Resource efficient plasmon-based 2D-photovoltaics with reflective support

For ultrathin (similar to 10 nm) nanocomposite films of plasmonic materials and semiconductors, the absorptance of normal incident light is typically limited to about 50%. However, through addition of a non-absorbing spacer with a highly reflective backside to such films, close to 100% absorptance can be achieved at a targeted wavelength. Here, a simple analytic model useful in the long wavelength limit is presented. It shows that the spectral response can largely be characterized in terms of two wavelengths, associated with the absorber layer itself and the reflective support, respectively. These parameters influence both absorptance peak position and shape. The model is employed to optimize the system towards broadband solar energy conversion, with the spectrally integrated plasmon induced semiconductor absorptance as a figure of merit. Geometries optimized in this regard are then evaluated in full finite element calculations which demonstrate conversion efficiencies of up to 64% of the Shockley-Queisser limit. This is achieved using only the equivalence of about 10 nanometer composite material, comprising Ag and a thin film solar cell layer of a-Si, CuInSe2 or the organic semiconductor MDMO-PPV. A potential for very resource efficient solar energy conversion based on plasmonics is thus demonstrated

Nitride semiconductors as carrier-selective contacts for silicon heterojunction solar cells

This work initially reports the electrical characterization of ZnSnxGe1-xN2 (ZTGN) layers (10% < < 90%) deposited on glass by combinatorial sputtering and further assesses the performance of silicon heterojunction (SHJ) solar cells featuring them as electron-selective contacts. Bandgap, dark conductivity, and the activation energy of the latter were found to significantly change between Sn and Ge-rich samples. When applying ZTGN layers as electron-selective contacts for SHJ solar cells, poor solar-cell performance was observed, with surprisingly similar results despite changes in material properties. From analysis and modelling of the current-voltage characteristics of several device structures, through a self-adaptive Differential Evolution algorithm, we show that the work function of the electron-selective contact lies around 4.35 eV for all investigated Sn and Ge contents, which is too high to form an excellent electron-selective contact. By comparing differ ent solar-cell architectures, we could further identify that the Ge-rich layer imposes an additional barrier to electron extraction, independently of its poor selectivity, due to its low conductivity. After having identified these loss mechanisms, MgSnN2 (MTN) was envisioned as a good candidate, due to its high electron concentration and bandgap at 50% Mg/(Mg+Sn) (at.%). Thus, we fabricated MTN layers also through a combinatorial sputtering approach, with no substrate heating and at 200 °C, resulting in MgxSn1-xN2 (43% < < 55%) samples, with bandgap around 2 eV, showing dark conductivity and activation energy that decreased towards Mg-rich samples. When applied to SHJ solar cells, JV characteristics similar to that when ZTGN was studied were obtained, and per formance was slightly better. The limiting properties were also of the same kind, with an estimated work function around 4.16 eV, shifting to 4.3 eV for samples grown at 200 °C, and Sn-rich samples showing a too high electron affinity. Mg-rich samples, as Ge-rich ones, resulted in strong s-shapes due to poor doping. Thus, doping these compounds with extrinsic elements appears as the most relevant approach to build efficient devices with a ZTGN or MTN contact layer.Este trabalho apresenta a caracterização elétrica de camadas de ZnSnxGe1-xN2 (ZTGN) (10% < x < 90%) depositadas em substrato de vidro por sputtering combinatório e avalia o desempenho de células solares de heterojunção de silício (SHJ) que apresentam essas camadas como contatos elétron-seletivos. Bandgap, condutividade e energia de ati vação variaram significantemente entre amostras ricas em Sn e Ge. Quando tais camadas foram aplicadas como contatos elétron-seletivos em células solares, os dispositivos apre sentaram baixo desempenho, com resultados surpreendentemente semelhantes apesar de mudanças nas propriedades do material. A partir de análises e modelagem das caracterís ticas corrente-tensão de várias estruturas de células solares, com auxílio de um algoritmo de Evolução Diferencial auto adaptativo, mostramos que a função trabalho do contato elétron-seletivo está em torno de 4.35 eV para todas as composições investigadas de Sn e Ge, o que é muito alto para formar um excelente contato. Através da comparação de diferentes arquiteturas de células solares, identificamos ainda que camadas ricas em Ge impõem uma barreira adicional à extração de elétrons, independentemente de sua baixa seletividade, devido a baixos valores de condutividade. Após a identificação desses mecan ismos de perdas, MgSnN2 (MTN) foi considerado como um bom candidato, já que apre senta bandgap adequado e alta concentração de elétrons para uma composição de 50% Mg/(Mg+Sn) (at.%). Desse modo, fabricamos camadas de MTN através de sputtering combinatório, sem aquecimento do substrato e à 200 °C, obtendo amostras de MgxSn1-xN2 (43% < x < 55%), com bandgap em torno de 2 eV, exibindo condutividade e energia de ativação que decrescem em amostras ricas em Mg. Características JV similares àque las observadas para ZTGN foram obtidas quando MTN foi empregado como camada elétron-seletiva, mas com desempenho ligeiramente superior. As propriedades limitantes foram as mesmas, com função trabalho estimada em 4.16 eV, aumentando para 4.3 eV para amostras fabricadas à 200 °C. Amostras ricas em Sn exibiram ainda alta afinidade eletrônica e aquelas ricas em Mg resultaram em curvas com severo perfil em “s” devido à baixa dopagem, como foi o caso de amostras de ZTGN ricas em Ge. Portanto, a dopagem desses materiais com elementos extrínsecos aparenta ser a abordagem mais relevante para a construção de dispositivos eficientes com contatos formados com camadas de ZTGN ou MTN

Reconfigurable Architectures and Systems for IoT Applications

abstract: Internet of Things (IoT) has become a popular topic in industry over the recent years, which describes an ecosystem of internet-connected devices or things that enrich the everyday life by improving our productivity and efficiency. The primary components of the IoT ecosystem are hardware, software and services. While the software and services of IoT system focus on data collection and processing to make decisions, the underlying hardware is responsible for sensing the information, preprocess and transmit it to the servers. Since the IoT ecosystem is still in infancy, there is a great need for rapid prototyping platforms that would help accelerate the hardware design process. However, depending on the target IoT application, different sensors are required to sense the signals such as heart-rate, temperature, pressure, acceleration, etc., and there is a great need for reconfigurable platforms that can prototype different sensor interfacing circuits. This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces. IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Efficient machine learning: models and accelerations

One of the key enablers of the recent unprecedented success of machine learning is the adoption of very large models. Modern machine learning models typically consist of multiple cascaded layers such as deep neural networks, and at least millions to hundreds of millions of parameters (i.e., weights) for the entire model. The larger-scale model tend to enable the extraction of more complex high-level features, and therefore, lead to a significant improvement of the overall accuracy. On the other side, the layered deep structure and large model sizes also demand to increase computational capability and memory requirements. In order to achieve higher scalability, performance, and energy efficiency for deep learning systems, two orthogonal research and development trends have attracted enormous interests. The first trend is the acceleration while the second is the model compression. The underlying goal of these two trends is the high quality of the models to provides accurate predictions. In this thesis, we address these two problems and utilize different computing paradigms to solve real-life deep learning problems. To explore in these two domains, this thesis first presents the cogent confabulation network for sentence completion problem. We use Chinese language as a case study to describe our exploration of the cogent confabulation based text recognition models. The exploration and optimization of the cogent confabulation based models have been conducted through various comparisons. The optimized network offered a better accuracy performance for the sentence completion. To accelerate the sentence completion problem in a multi-processing system, we propose a parallel framework for the confabulation recall algorithm. The parallel implementation reduce runtime, improve the recall accuracy by breaking the fixed evaluation order and introducing more generalization, and maintain a balanced progress in status update among all neurons. A lexicon scheduling algorithm is presented to further improve the model performance. As deep neural networks have been proven effective to solve many real-life applications, and they are deployed on low-power devices, we then investigated the acceleration for the neural network inference using a hardware-friendly computing paradigm, stochastic computing. It is an approximate computing paradigm which requires small hardware footprint and achieves high energy efficiency. Applying this stochastic computing to deep convolutional neural networks, we design the functional hardware blocks and optimize them jointly to minimize the accuracy loss due to the approximation. The synthesis results show that the proposed design achieves the remarkable low hardware cost and power/energy consumption. Modern neural networks usually imply a huge amount of parameters which cannot be fit into embedded devices. Compression of the deep learning models together with acceleration attracts our attention. We introduce the structured matrices based neural network to address this problem. Circulant matrix is one of the structured matrices, where a matrix can be represented using a single vector, so that the matrix is compressed. We further investigate a more flexible structure based on circulant matrix, called block-circulant matrix. It partitions a matrix into several smaller blocks and makes each submatrix is circulant. The compression ratio is controllable. With the help of Fourier Transform based equivalent computation, the inference of the deep neural network can be accelerated energy efficiently on the FPGAs. We also offer the optimization for the training algorithm for block circulant matrices based neural networks to obtain a high accuracy after compression