The SAMPIC Waveform and Time to Digital Converter

Sce ElectroniqueInternational audienceSAMPIC is a Waveform and Time to DigitalConverter (WTDC) multichannel chip. Each of its 16 channelsassociates a DLL-based TDC providing a raw time with an ultrafastanalog memory allowing fine timing extraction as well asother parameters of the pulse. Each channel also integrates adiscriminator that can trigger itself independently or participateto a more complex trigger. After triggering, analog data isdigitized by an on-chip ADC and only that corresponding to aregion of interest is sent serially to the DAQ. The association ofthe raw and fine timings permits achieving timing resolutions of afew ps rms. The paper describes the detailed SAMPIC0architecture and reports its main measured performances

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Development of a Waveform Sampling ASIC with Femtosecond Timing for a Low Occupancy Vertex Detector.

Ph.D. Thesis. University of Hawaiʻi at Mānoa 2018

Development of high speed integrated circuit for very high resolution timing measurements

A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption

14-Bit and 2GS/s Low Power Digitizing Boards for Physics Experiments

International audienceThe trend in data acquisition systems for modern physics experiments is to digitize analog signals closer and closer to the detector. The digitization systems have followed the progress of commercial analog to digital converters. The state of the art for these devices is currently 200 MSample/s for a 14-bit range. The new boards, described in this paper, have been designed to improve these performances by more than an order of magnitude. This board mainly includes 4 channels sampling analog data up to 2 GSamples/s with an analog bandwidth of 300 MHz, and digitizing it with a 14-bit dynamic range. It is based on the custom-designed MATACQ chip. The latter's innovative design permits reaching these performances with power consumption smaller than 1W, thus allowing a total consumption below 20W for the whole board. The board is triggerable either by internal or external signals and several boards are easily synchronizable. The board integrates USB, GPIB and VME interfaces that permit a readout speed of up to 500 events/s with the whole memory depth of the 4 channels read

Digital signal processing for segmented HPGe detectors preprocessingalgorithms and pulse shape analysis

MINIBALL is an versatile spectrometer consisting of 24 longitudinally six-fold segmented HPGe detectors, build for the efficient detection of rare γ decays in nuclear reactions of radioactive ion beams. MINIBALL was the first spectrometer equipped with digital electronics. Pulse shape analysis algorithms to determine the interaction position of γ -rays were implemented on a Digital Signal Processor and validated in an experiment using a collimated γ -ray source. Emphasis was placed on the properties of the different digital signal processing algorithms, the consequences for the implementation and the applicability for position determination. The next generation of γ -ray spectrometers will consist of highly segmented HPGe detectors equipped with digital electronics, resulting in a more than ten-fold increase in complexity compared to current spectrometers. To enable the construction of a γ -ray tracking spectrometer, new and powerful digital electronics will be developed. Preprocessing algorithms, giving the γ -ray energy and generating event triggers, were implemented on a VME module equipped with fast A/D converters and tested with different detectors and sources. Emphasis was placed on the detailed simulation and understanding of the algorithms as well as the influence of electronics and detector onto the energy resolution

Intersatellite clock synchronization and absolute ranging for gravitational wave detection in space

The Laser Interferometer Space Antenna (LISA) is a European Space Agency (ESA) large-scale space mission, aiming to detect gravitational waves (GWs) in the observation band of 0.1mHz to 1Hz. The constellation is formed by three spacecrafts (SCs), exchanging laser beams with each other. The detector adopts heterodyne interferometry with MHz frequency offsets. GW signals are then encoded in optical beatnote phases, and the phase information has to be extracted by a core device called phasemeter (PM). Unequal and time- varying orbital motions introduce an overwhelming laser noise coupling that impedes the LISA performance levels of 10 ucycle/sqrt(Hz). Thereby, the post-processing technique called time-delay interferometry (TDI) time-shifts phase signals to synthesize virtual equal-arm interferometers. TDI requires absolute-ranging information, as its input, to the accuracy of 1 m rms, which will be provided by monitors like pseudo-random noise ranging (PRNR) and time-delay interferometry ranging (TDIR). An additional challenge is independent clocks on each SC that time-stamp PM data. This, alongside TDI, requires the synchronization of the onboard clocks in post-processing. This thesis reports on the experimental demonstrations of such key components for LISA. This is done by extending the scope of the hexagonal optical testbed at the Albert Einstein Institute (AEI): the "Hexagon". The first part of the thesis focuses on clock synchronization, utilizing the TDIR-like algorithm. With representative technologies both in devices and data analysis, this shows a new benchmark performance of LISA clock synchronization, achieving a 1 ucycle/sqrt(Hz) mark above 60 mHz and a TDIR accuracy of 1.84 m in range. This part also includes the first-ever verification of three noise couplings stemming from TDI and clock synchronization in an optical experiment. The second part of the thesis evolves the Hexagon further with PRNR. It commences with a review of the latest development using a transmission/reception loopback on a single hardware platform. This is followed by the research on the impact of the pseudo-random noise (PRN) modulation on phase tracking. This reveals that the codes, used at best knowledge so far, hinder the carrier phase extraction from achieving the 1 ucycle/sqrt(Hz) mark with realistic data encoded for intersatellite data communication. Some adaptations of PRN codes are proposed, and it is shown that these offer enough suppression of the noise coupling into phase tracking. After phase tracking is confirmed to be compatible with PRN modulations, PRNR itself is inves- tigated. The key novelty of this thesis in terms of PRNR is the study of its absolute-ranging feature, while previous research on this technology focused on stochastic noise properties. This requires the resolution of PRNR ambiguity and the correction of ranging biases. There suggests that the PRNR estimate, alongside some calibrations, can constantly function as absolute ranging with sub-meter accuracy

Preliminary characterisation measurements of CERN picoTDC

In questa tesi sono presentate misure preliminari per valutare le prestazioni di un nuovo ASIC TDC sviluppato dal CERN (picoTDC) al fine di valutarne l'idoneità per l'implementazione all'interno del rilevatore TOF di ALICE. La parziale sostituzione dell'attuale HPTDC con il picoTDC comporterebbe, oltre al rinnovo dei componenti delle schede di lettura TDC sviluppate circa 20 anni fa, la semplificazione dell'architettura complessiva, consentendo l'integrazione di 64 canali per chip anziché gli 8 attuali dell'HPTDC. Per raggiungere questo obiettivo, sono stati eseguiti test mirati per valutare la risoluzione, la non linearità differenziale e la capacità di risposta ai segnali forniti dalla NINO FEA, la scheda di front-end del rivelatore TOF, del picoTDC. Dopo una breve introduzione alle varie tipologie di Analog to Digital Converter (ADC) e Time to Digital Converter (TDC), vengono presentate l'architettura del picoTDC e la configurazione sperimentale utilizzata, seguite dall'illustrazione dell'attività di ricerca condotta in laboratorio. I dati ottenuti hanno evidenziato una buona risoluzione del dispositivo (inferiore a 5 ps) e una notevole compatibilità con la scheda di front-end del rivelatore di ALICE. Tuttavia, i test sulla non linearità differenziale hanno mostrato risultati ancora insoddisfacenti. Pertanto, per il futuro, sarà necessario svolgere ulteriori approfondimenti al fine di migliorare la configurazione del chip