High-speed digital filtering: Structures and finite wordlength effects

This paper is a study of high-throughput filter structures such as block structures and their behavior in finite precision environments. Block structures achieve high throughput rates by using a large number of processors working in parallel. It has been believed that block structures which are relatively robust to round-off noise must also be robust to coefficient quantization errors. However, our research has shown that block structures, in fact, have high coefficient sensitivity. A potential problem that arises as a result of coefficient quantization is a periodically time-varying behavior exhibited by the realized filter. We will demonstrate how finite wordlength errors can change a nominally time-invariant filter into a time-varying system. We will identify the block structures that have low coefficient sensitivity, and develop high-speed structures that are immune to the time-varying problems caused by coefficient quantization.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/41355/1/11265_2004_Article_BF00930646.pd

Digital Filters

The new technology advances provide that a great number of system signals can be easily measured with a low cost. The main problem is that usually only a fraction of the signal is useful for different purposes, for example maintenance, DVD-recorders, computers, electric/electronic circuits, econometric, optimization, etc. Digital filters are the most versatile, practical and effective methods for extracting the information necessary from the signal. They can be dynamic, so they can be automatically or manually adjusted to the external and internal conditions. Presented in this book are the most advanced digital filters including different case studies and the most relevant literature

A Low-memory Spectral-correlation Analyzer For Digital Qam-srrc Waveforms

Cyclostationary signal processing (CSP) provides the ability to estimate received waveforms’ statistical features blindly. Quadrature amplitude modulated (QAM) waveforms, when filtered by the square-root-raised cosine (SRRC) pulse shape function, have cyclic features that CSP can exploit to detect waveform parameters such as symbol rate (SR) and center frequency (CF). The estimation of these SR-CF pairs enables a cognitive radio (CR) to perform spectrum sensing techniques such as spectrum sharing and interference mitigation. Here, we investigate a field-programmable gate array (FPGA) application of a blind symbol rate-center frequency estimator. First, this study provides a background on the theory behind the cyclic spectral density function (CSD), spectral correlation analyzers (SCA), and spectrum sensing. Following this is a discussion on the motivation for CubeSat spectrum sensing. An SCA implementation for low-memory devices, such as FPGA-based CubeSat, is then describes. The paper concludes by reporting the performance characteristics of the newly developed streaming-based SCA

Finite worldlength effects in fixed-point implementations of linear systems

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 173-194).by Vinay Mohta.M.Eng

Optimization of a hardware/software coprocessing platform for EEG eyeblink detection and removal

The feasibility of implementing a real-time system for removing eyeblink artifacts from electroencephalogram (EEG) recordings utilizing a hardware/software coprocessing platform was investigated. A software based wavelet and independent component analysis (ICA) eyeblink detection and removal process was extended to enable variation in its processing parameters. Exploiting the efficiency of hardware and the reconfigurability of software, it was ported to a field programmable gate array (FPGA) development platform which was found to be capable of implementing the revised algorithm, although not in real-time. The implemented hardware and software solution was applied to a collection of both simulated and clinically acquired EEG data with known artifact and waveform characteristics to assess its speed and accuracy. Configured for optimal accuracy in terms of minimal false positives and negatives as well as maintaining the integrity of the underlying EEG, especially when encountering EEG waveform patterns with an appearance similar to eyeblink artifacts, the system was capable of processing a 10 second EEG epoch in an average of 123 seconds. Configured for efficiency, but with diminished accuracy, the system required an average of 34 seconds. Varying the ICA contrast function showed that the gaussian nonlinearity provided the best combination of reliability and accuracy, albeit with a long execution time. The cubic nonlinearity was fast, but unreliable, while the hyperbolic tangent contrast function frequently diverged. It is believed that the utilization of programmable logic with increased logic capacity and processing speed may enable this approach to achieve the objective of real-time operation

Design and Implementation of a Re-Configurable Arbitrary Signal Generator and Radio Frequency Spectrum Analyser

This research is focused on the design, simulation and implementation of a reconfigurable arbitrary signal generator and the design, simulation and implementation of a radio frequency spectrum analyser based on digital signal processing. Until recently, Application Specific Integrated Circuits (ASICs) were used to produce high performance re-configurable function and arbitrary waveform generators with comprehensive modulation capabilities. However, that situation is now changing with the availability of advanced but low cost Field Programmable Gate Arrays (FPGAs), which could be used as an alternative to ASICs in these applications. The availability of high performance FPGA families opens up the opportunity to compete with ASIC solutions at a fraction of the development cost of an ASIC solution. A fast digital signal processing algorithm for digital waveform generation, using primarily but not limited to Direct Digital Synthesis (DDS) technologies, developed and implemented in a field-configurable logic, with control provided by an embedded microprocessor replacing a high cost ASIC design appeared to be a very attractive concept. This research demonstrates that such a concept is feasible in its entirety. A fully functional, low-complexity, low cost, pulse, Gaussian white noise and DDS based function and arbitrary waveform generator, capable of being amplitude, frequency and phase modulated by an internally generated or external modulating signal was implemented in a low-cost FPGA. The FPGA also included the capabilities to perform pulse width modulation and pulse delay modulation on pulse waveforms. Algorithms to up-convert the sampling rate of the external modulating signal using Cascaded Integrator Comb (CIC) filters and using interpolation method were analysed. Both solutions were implemented to compare their hardware complexities. Analysis of generating noise with user-defined distribution is presented. The ability of triggering the generator by an internally generated or an external event to generate a burst of waveforms where the time between the trigger signal and waveform output is fixed was also implemented in the FPGA. Finally, design of interface to a microprocessor to provide control of the versatile waveform generator was also included in the FPGA. This thesis summarises the literature, design considerations, simulation and implementation of the generator design. The second part of the research is focused on radio frequency spectrum analysis based on digital signal processing. Most existing spectrum analysers are analogue in nature and their complexity increases with frequency. Therefore, the possibility of using digital techniques for spectrum analysis was considered. The aim was to come up with digital system architecture for spectrum analysis and to develop and implement the new approach on a suitable digital platform. This thesis analyses the current literature on shifting algorithms to remove spurious responses and highlights its drawbacks. This thesis also analyses existing literature on quadrature receivers and presents novel adaptation of the existing architectures for application in spectrum analysis. A wide band spectrum analyser receiver with compensation for gain and phase imbalances in the Radio Frequency (RF) input range, as well as compensation for gain and phase imbalances within the Intermediate Frequency (IF) pass band complete with Resolution Band Width (RBW) filtering, Video Band Width (VBW) filtering and amplitude detection was implemented in a low cost FPGA. The ability to extract the modulating signal from a frequency or amplitude modulated RF signal was also implemented. The same family of FPGA used in the generator design was chosen to be the digital platform for this design. This research makes arguments for the new architecture and then summarises the literature, design considerations, simulation and implementation of the new digital algorithm for the radio frequency spectrum analyser

Multicarrier Faster-than-Nyquist Signaling Transceivers: From Theory to Practice

The demand for spectrum resources in cellular systems worldwide has seen a tremendous escalation in the recent past. The mobile phones of today are capable of being cameras taking pictures and videos, able to browse the Internet, do video calling and much more than an yesteryear computer. Due to the variety and the amount of information that is being transmitted the demand for spectrum resources is continuously increasing. Efficient use of bandwidth resources has hence become a key parameter in the design and realization of wireless communication systems. Faster-than-Nyquist (FTN) signaling is one such technique that achieves bandwidth efficiency by making better use of the available spectrum resources at the expense of higher processing complexity in the transceiver. This thesis addresses the challenges and design trade offs arising during the hardware realization of Faster-than-Nyquist signaling transceivers. The FTN system has been evaluated for its achievable performance compared to the processing overhead in the transmitter and the receiver. Coexistence with OFDM systems, a more popular multicarrier scheme in existing and upcoming wireless standards, has been considered by designing FTN specific processing blocks as add-ons to the conventional transceiver chain. A multicarrier system capable of operating under both orthogonal and FTN signaling has been developed. The performance of the receiver was evaluated for AWGN and fading channels. The FTN system was able to achieve 2x improvement in bandwidth usage with similar performance as that of an OFDM system. The extra processing in the receiver was in terms of an iterative decoder for the decoding of FTN modulated signals. An efficient hardware architecture for the iterative decoder reusing the FTN specific processing blocks and realize different functionality has been designed. An ASIC implementation of this decoder was implemented in a 65nm CMOS technology and the implemented chip has been successfully verified for its functionality

Structure-Preserving Model Reduction of Physical Network Systems

This paper considers physical network systems where the energy storage is naturally associated to the nodes of the graph, while the edges of the graph correspond to static couplings. The first sections deal with the linear case, covering examples such as mass-damper and hydraulic systems, which have a structure that is similar to symmetric consensus dynamics. The last section is concerned with a specific class of nonlinear physical network systems; namely detailed-balanced chemical reaction networks governed by mass action kinetics. In both cases, linear and nonlinear, the structure of the dynamics is similar, and is based on a weighted Laplacian matrix, together with an energy function capturing the energy storage at the nodes. We discuss two methods for structure-preserving model reduction. The first one is clustering; aggregating the nodes of the underlying graph to obtain a reduced graph. The second approach is based on neglecting the energy storage at some of the nodes, and subsequently eliminating those nodes (called Kron reduction).</p