Programmable active pixel sensor to investigate neural interactions within the retina

Detection of the visual scene by the eye and the resultant neural interactions of the retina-brain system give us our perception of sight. We have developed an Active Pixel Sensor (APS) to be used as a tool for both furthering understanding of these interactions via experimentation with the retina and to make developments towards a realisable retinal prosthesis. The sensor consists of 469 pixels in a hexagonal array. The pixels are interconnected by a programmable neural network to mimic lateral interactions between retinal cells. Outputs from the sensor are in the form of biphasic current pulse trains suitable to stimulate retinal cells via a biocompatible array. The APS will be described with initial characterisation and test results

Monolithic Perimeter Gated Single Photon Avalanche Diode Based Optical Detector in Standard CMOS

Since the 1930\u27s photomultiplier tubes (PMTs) have been used in single photon detection. Single photon avalanche diodes (SPADs) are p-n junctions operated in the Geiger mode. Unlike PMTs, CMOS based SPADs are smaller in size, insensitive to magnetic fields, less expensive, less temperature dependent, and have lower bias voltages. Using appropriate readout circuitry, they measure properties of single photons, such as energy, arrival time, and spatial path making them excellent candidates for single photon detection. CMOS SPADs suffer from premature breakdown due to the non-uniform distribution of the electric field. This prevents full volumetric breakdown of the device and reduces the detection effciency by increasing the noise. A novel device known as the perimeter gated SPAD (PGSPAD) is adopted in this dissertation for mitigating the premature perimeter breakdown without compromising the fill-factor of the device. The novel contributions of this work are as follows. A novel simulation model, including SPICE characteristics and the stochastic behavior, has been developed for the perimeter gated SPAD. This model has the ability to simulate the static current-voltage and dynamic response characteristics. It also simulates the noise and spectral response. A perimeter gated silicon photomultiplier, with improved signal to noise ratio, is reported for the first time. The gate voltage reduces the dark current of the silicon photomultiplier by preventing the premature breakdown. A digital SPAD with the tunable dynamic range and sensitivity is demonstrated for the first time. This pixel can be used for weak optical signal application when relatively higher sensitivity and lower input dynamic range is required. By making the sensitivity-dynamic range trade-off the same detector can be used for applications with relatively higher optical power. Finally, an array has been developed using the digital silicon photomultiplier in which the dead time of the pixels have been reduced. This digital photomultiplier features noise variation compensation between the pixels

Wide-Dynamic Range Image Sensor Prototype Based On Digital Readout Integrated Circuit

Emerging infrared and visible imaging applications require higher sensitivity, larger pixel array, larger contrast ratio (dynamic range), very low power consumption and faster data readout rate operations all at the same time. Some of these applications are camera surveillance used both in day/night (very bright and dark conditions), medical diagnostics, weather forecasting, and aerial search & rescue operations etc. The digital-pixel focal plane array (DFPA) implemented in this thesis has the capabilities to capture a wide dynamic range of more than 120dB in a single global shutter without saturating the pixels at a huge frame rate of more than 500Hz. An adaptive Integration Window technique has been developed which ensures that we are able to measure such a huge dynamic range using a counter of only 10 bits (this helps us lower the power consumption of the design). This proposed image sensor has been designed, fabricated and tested in 65nm CMOS technology. It has 16 x 16-pixel array with 16 x 9 pixels with an inbuilt Silicon APD for optical testing and 16 x 7 dummy pixels for electrical testing. Our design proposes an off-chip digital calibration technique to cut down the burden on the analog circuitry. The sensor design achieved more than 128dB+ of dynamic range with a DNL/INL of 0.65/1.65 respectively with a power consumption of only 0.58 uW/pixel. The digital calibration scheme successfully cuts down the pixel-pixel variation standard deviations by a factor of 4. The proposed image sensor design should be able to address most of the short-comings of conventional FPAs and provides a one-shot solution to the design of high performance CMOS image sensors

Analysis and design of a wide dynamic range pulse-frequency modulation CMOS image sensor

Complementary Metal-Oxide Semiconductor (CMOS) image sensor is the dominant electronic imaging device in many application fields, including the mobile or portable devices, teleconference cameras, surveillance and medical imaging sensors. Wide dynamic range (WDR) imaging is of interest particular, demonstrating a large-contrast imaging range of the sensor. As of today, different approaches have been presented to provide solutions for this purpose, but there exists various trade-offs among these designs, which limit the number of applications. A pulse-frequency modulation (PFM) pixel offers the possibility to outperform existing designs in WDR imaging applications, however issues such as uniformity and cost have to be carefully handled to make it practical for different purposes. In addition, a complete evaluation of the sensor performance has to be executed prior to fabrication in silicon technology. A thorough investigation of WDR image sensor based on the PFM pixel is performed in this thesis. Starting with the analysis, modeling, and measurements of a PFM pixel, the details of every particular circuit operation are presented. The causes of dynamic range (DR) limitations and signal nonlinearity are identified, and noise measurement is also performed, to guide future design strategies. We present the design of an innovative double-delta compensating (DDC) technique which increases the sensor uniformity as well as DR. This technique achieves performance optimization of the PFM pixel with a minimal cost an improved linearity, and is carefully simulated to demonstrate its feasibility. A quad-sampling technique is also presented with the cooperation of pixel and column circuits to generate a WDR image sensor with a reduced cost for the pixel. This method, which is verified through the field-programmable gate array (FPGA) implementation, saves considerable area in the pixel and employs the maximal DR that a PFM pixel provides. A complete WDR image sensor structure is proposed to evaluate the performance and feasibility of fabrication in silicon technology. The plans of future work and possible improvements are also presented