Miniaturized Silicon Photodetectors

Silicon (Si) technologies provide an excellent platform for the design of microsystems where photonic and microelectronic functionalities are monolithically integrated on the same substrate. In recent years, a variety of passive and active Si photonic devices have been developed, and among them, photodetectors have attracted particular interest from the scientific community. Si photodiodes are typically designed to operate at visible wavelengths, but, unfortunately, their employment in the infrared (IR) range is limited due to the neglectable Si absorption over 1100 nm, even though the use of germanium (Ge) grown on Si has historically allowed operations to be extended up to 1550 nm. In recent years, significant progress has been achieved both by improving the performance of Si-based photodetectors in the visible range and by extending their operation to infrared wavelengths. Near-infrared (NIR) SiGe photodetectors have been demonstrated to have a “zero change” CMOS process flow, while the investigation of new effects and structures has shown that an all-Si approach could be a viable option to construct devices comparable with Ge technology. In addition, the capability to integrate new emerging 2D and 3D materials with Si, together with the capability of manufacturing devices at the nanometric scale, has led to the development of new device families with unexpected performance. Accordingly, this Special Issue of Micromachines seeks to showcase research papers, short communications, and review articles that show the most recent advances in the field of silicon photodetectors and their respective applications

Direct integration of micro-LEDs and a SPAD detector on a silicon CMOS chip for data communications and time-of-flight ranging

We present integration of singulated micron-sized light emitting diodes (micro-LEDs) directly onto a silicon CMOS drive chip using a transfer printing method. An 8x8 micro-LED device array with individual control over each pixel is demonstrated with modulation bandwidths up to 50 MHz, limited by the large modulation depth of the driver chip. The 2 kHz frame rate CMOS driver also incorporates a Single Photon Avalanche Diode device thus allowing detection and transmission functionality on a single integrated chip. Visible light communications at data rates up to 1 Mbps, and time-of-flight ranging with cm-scale resolution are demonstrated using this hybrid integrated system

ASIC-enabled High Resolution Optical Time Domain Reflectometer

Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks.The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber.To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and (5) conclusion. Thus, it begins by providing background, basic OTDR operation, overview of ASIC functionality, and past experiments done with the ASIC for multimode fiber. Chapter 2 begins the investigation of a high resolution OTDR for single mode fiber. A though explanation of how the OTDR ASIC operates is presented in this chapter, as well as details on the OTDR scheme that has been implemented. Chapter 3 analyzes the performance of the OTDR. Chapter 4 introduces a hybrid silicon semiconductor optical amplifier and discusses its theoretical implication on the OTDR in terms of improving receiver sensitivity. Lastly, a summary of the findings and discussion of other applications lie in Chapter 5

On-Chip Integrated Functional Near Infra-Red Spectroscopy (fNIRS) Photoreceiver for Portable Brain Imaging

RÉSUMÉ L'imagerie cérébrale fonctionnelle utilisant la Spectroscopie Fonctionnelle Proche-Infrarouge (SFPI) propose un outil portatif et non invasif de surveillance de l'oxygénation du sang. SFPI est une technique de haute résolution temporelle non invasive, sûr, peu intrusive en temps réel et pour l'imagerie cérébrale à long terme. Il permet de détecter des signaux hémodynamiques à la fois rapides et neuronaux ou lents. Outre les avantages importants des systèmes SFPI, ils souffrent encore de quelques inconvénients, notamment d’une faible résolution spatiale, d’un bruit de niveau modérément élevé et d’une grande sensibilité au mouvement. Afin de surmonter les limites des systèmes actuellement disponibles de SFPI non-portables, dans cette thèse, nous en avons introduit une nouvelle de faible puissance, miniaturisée sur une puce photodétecteur frontal destinée à des systèmes de SFPI portables. Elle contient du silicium photodiode à avalanche (SiAPD), un amplificateur de transimpédance (TIA), et « Quench-Reset », circuits mis en oeuvre en utilisant les technologies CMOS standards pour fonctionner dans les deux modes : linéaire et Geiger. Ainsi, elle peut être appliquée pour les deux fNIRS : en onde continue (CW- SFPI) et pour des applications de comptage de photon unique. Plusieurs SiAPDs ont été mises en oeuvre dans de nouvelles structures et formes (rectangulaires, octogonales, double APDs, imbriquées, netted, quadratiques et hexadecagonal) en utilisant différentes techniques de prévention de la dégradation de bord prématurée. Les principales caractéristiques des SiAPDs sont validées et l'impact de chaque paramètre ainsi que les simulateurs de l'appareil (TCAD, COMSOL, etc) ont été étudiés sur la base de la simulation et de mesure des résultats. Proposées SiAPDs techniques d'exposition avec un gain de grande avalanche, tension faible ventilation et une grande efficacité de détection des photons dans plus de faibles taux de comptage sombres. Trois nouveaux produits à haut gain, bande passante (GBW) et à faible bruit TIA sont introduits basés sur le concept de gain distribué, d’amplificateur logarithmique et sur le rejet automatique du bruit pour être appliqué en mode de fonctionnement linéaire. Le TIA proposé offre une faible consommation, un gain de haute transimpédance, une bande passante ajustable et un très faible bruit d'entrée et de sortie. Le nouveau circuit mixte trempe-reset (MQC) et un MQC contrôlable (CMQC) frontaux offrent une faible puissance, une haute vitesse de comptage de photons avec un commandable de temps de hold-off et temps de réinitialiser. La première intégration sur puce de SiAPDs avec TIA et Photon circuit de comptage a été démontrée et montre une amélioration de l'efficacité de la photodétection, spécialement en ce qui concerne la sensibilité, la consommation d'énergie et le rapport signal sur bruit.----------ABSTRACT Optical brain imaging using functional near infra-red spectroscopy (fNIRS) offers a direct and noninvasive tool for monitoring of blood oxygenation. fNIRS is a noninvasive, safe, minimally intrusive, and high temporal-resolution technique for real-time and long-term brain imaging. It allows detecting both fast-neuronal and slow-hemodynamic signals. Besides the significant advantages of fNIRS systems, they still suffer from few drawbacks including low spatial- resolution, moderately high-level noise and high-sensitivity to movement. In order to overcome the limitations of currently available non-portable fNIRS systems, we have introduced a new low-power, miniaturized on-chip photodetector front-end intended for portable fNIRS systems. It includes silicon avalanche photodiode (SiAPD), Transimpedance amplifier (TIA), and Quench- Reset circuitry implemented using standard CMOS technologies to operate in both linear and Geiger modes. So it can be applied for both continuous-wave fNIRS (CW-fNIRS) and also single-photon counting applications. Several SiAPDs have been implemented in novel structures and shapes (Rectangular, Octagonal, Dual, Nested, Netted, Quadratic and Hexadecagonal) using different premature edge breakdown prevention techniques. The main characteristics of the SiAPDs are validated and the impact of each parameter and the device simulators (TCAD, COMSOL, etc.) have been studied based on the simulation and measurement results. Proposed techniques exhibit SiAPDs with high avalanche-gain (up to 119), low breakdown-voltage (around 12V) and high photon-detection efficiency (up to 72% in NIR region) in additional to a low dark- count rate (down to 30Hz at 1V excess bias voltage). Three new high gain-bandwidth product (GBW) and low-noise TIAs are introduced and implemented based on distributed-gain concept, logarithmic-amplification and automatic noise-rejection and have been applied in linear-mode of operation. The implemented TIAs offer a power-consumption around 0.4 mW, transimpedance gain of 169 dBΩ, and input-output current/voltage noises in fA/pV range accompanied with ability to tune the gain, bandwidth and power-consumption in a wide range. The implemented mixed quench-reset circuit (MQC) and controllable MQC (CMQC) front-ends offer a quenchtime of 10ns, a maximum power-consumption of 0.4 mW, with a controllable hold-off and resettimes. The on-chip integration of SiAPDs with TIA and photon-counting circuitries has been demonstrated showing improvement of the photodetection-efficiency, specially regarding to the sensitivity, power-consumption and signal-to-noise ratio (SNR) characteristics

Design of Pixellated CMOS Photon Detector for Secondary Electron Detection in the Scanning Electron Microscope

This paper presents a novel method of detecting secondary electrons generated in the scanning electron microscope (SEM). The method suggests that the photomultiplier tube (PMT), traditionally used in the Everhart-Thornley (ET) detector, is to be replaced with a configurable multipixel solid-state photon detector offering the advantages of smaller dimension, lower supply voltage and power requirements, and potentially cheaper product cost. The design of the proposed detector has been implemented using a standard 0.35 μm CMOS technology with optical enhancement. This microchip comprises main circuit constituents of an array of photodiodes connecting to respective noise-optimised transimpedance amplifiers (TIAs), a selector-combiner (SC) circuit, and a postamplifier (PA). The design possesses the capability of detecting photons with low input optical power in the range of 1 nW with 100 μm × 100 μm sized photodiodes and achieves a total amplification of 180 dBΩ at the output.Peer Reviewe

Energy-Efficient Receiver Design for High-Speed Interconnects

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1E−12 at −16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s. Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1E−12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency. Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.</p

An overview of lidar imaging systems for autonomous vehicles

Lidar imaging systems are one of the hottest topics in the optronics industry. The need to sense the surroundings of every autonomous vehicle has pushed forward a race dedicated to deciding the final solution to be implemented. However, the diversity of state-of-the-art approaches to the solution brings a large uncertainty on the decision of the dominant final solution. Furthermore, the performance data of each approach often arise from different manufacturers and developers, which usually have some interest in the dispute. Within this paper, we intend to overcome the situation by providing an introductory, neutral overview of the technology linked to lidar imaging systems for autonomous vehicles, and its current state of development. We start with the main single-point measurement principles utilized, which then are combined with different imaging strategies, also described in the paper. An overview of the features of the light sources and photodetectors specific to lidar imaging systems most frequently used in practice is also presented. Finally, a brief section on pending issues for lidar development in autonomous vehicles has been included, in order to present some of the problems which still need to be solved before implementation may be considered as final. The reader is provided with a detailed bibliography containing both relevant books and state-of-the-art papers for further progress in the subject.Peer ReviewedPostprint (published version