Concurrent Dual Band Radio-over-Fiber Transmission Using 1-bit Envelope Delta-Sigma Modulation

With the growing demand for bandwidth and transmission speed, mobile communication network designs must stay adaptable, efficient and cost-effective. A key integration has been Radio-over-Fiber (RoF) transmission systems that provide a cheaper option and low loss for high frequency signal transfer. For the optical transmitter, delta-sigma modulation (DSM) can be a beneficial addition. The partnership simplifies the Digital-Radio-over-Fiber setup by removing the need for additional converters and prompts adjustments based on system need. Main factors in delta-sigma modulators are the amount of quantization bits and the order of the modulator. Changing quantization bits to a single bit allows the system to use less processing bandwidth and less error experienced from optical transmission. High order structures provide more noise shaping to shift noise away from the band of interest. Still, such setups are prone to linearity problems due to clock jitter from multiple feedback loops. Different adaptations of delta-sigma modulation have been designed to combat the problems, but a key standout is the implementation of an envelope delta-sigma modulation (EDSM). Envelope delta-sigma modulation’s separate processing of envelope and phase delivers time alignment and noise shaping counter the negative implications from high order DSMs. Combining envelope delta-sigma modulation with RoF transmission is an attractive option, but research has yet to delve into carrier aggregation with these setups. This thesis explores concurrent dual band 64-QAM 20 MHz LTE Radio-over-Fiber using 1-bit envelope delta-sigma modulation. It expands transmitter functionality by concurrent signal integration. Inside the EDSM is a 4th order bandpass delta-sigma modulator custom tailored one of two carrier frequencies. The two frequencies come from two different LTE bands to show interband compatibility. The carrier frequencies are 2.112 GHz from LTE band 1 and 2.64 GHz from LTE band 7. Simulation and experimental results confirm the functionality of the proposed envelope delta-sigma modulation RoF system in single and dual band for LTE standards (error vector magnitude < 8%). Experimental results confirm that EDSM is more resilient to RoF transmission than BP-DSM. However, the EVM values for BP-DSM are better for carrier aggregated transmission

Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

Quadrature sigma-delta modulators for reconfigurable A/D interface and dynamic spectrum access: analysis, design principles and digital post-processing

In the course of development of wireless communications and its modern applications, such as cloud technologies and increased consumption and sharing of multimedia, the radio spectrum has become increasingly congested. However, temporarily and spatially underused spectrum exists at the same time. For increasing the efficiency of spectrum usage, the concept of dynamic spectrum access (DSA) has been proposed. Ultimately, the DSA principle should be exploited also in cognitive radio (CR) receivers. Herein, this paradigm is approached from the receiver architecture point-of-view, considering software-defined radio (SDR) as a platform for the future DSA and CR devices. Particularly, an analog-to-digital converter (ADC) architecture exploiting quadrature ΣΔ modulator (QΣΔM) is studied in detail and proposed as a solution for the A/D interface, being identified as a performance bottleneck in SDRs. By exploiting a complex valued noise transfer function (NTF) enabled by the QΣΔM, the quantization precision of the ADC can be efficiently and flexibly focused on the frequency channels and the signals to be received and detected. At the same time, with a traditional non-noise-shaping ADC, the precision is distributed equally for the whole digitized frequency band containing also noninteresting signals. With a single QΣΔM, it is also possible to design a multiband NTF, allowing reception of multiple noncontiguous frequency channels without parallel receiver chains. Furthermore, with the help of digital control, the QΣΔM response can be reconfigured during operation. These capabilities fit in especially well with the above mentioned DSA and CR schemes, where the temporarily and spatially available channels might be scattered in frequency. From the implementation point-of-view, the effects of inherent implementation inaccuracies in the QΣΔM design need to be thoroughly understood. In this thesis, novel closed-form matrix-algebraic expressions are presented for analyzing the transfer functions of a general multistage QΣΔM with arbitrary number of arbitrary-order stages. Altogether, the signal response of an I/Q mismatched QΣΔM has four components. These are the NTF, an image noise transfer function, a signal transfer function (STF) and an image signal transfer function. The image transfer functions are provoked by the I/Q mismatches and define the frequency profile of the generated mirror-frequency interference (MFI), potentially deteriorating the quality of the received signal. This contribution of the thesis increases the understanding of different QΣΔM structures and allows the designers to study the effects of the implementation inaccuracies in closed form. In order to mitigate the MFI and improve the signal reception, a mirror-frequency rejecting STF design is proposed herein. This design is found to be effective against I/Q mismatches taking place in the feedback branches of the QΣΔM. This is shown with help of the closed-form analysis and confirmed with computer simulations on realistic reception scenarios. When a mismatch location independent MFI suppression is the desired option, it is a logical choice to do this processing in a digital domain, after the whole analog receiver front-end. However, this sets demands for the information to be digitized, i.e., the source of the MFI should be available also in the digital domain. For this purpose, a novel multiband transfer function design is proposed herein. In addition, a QΣΔM specific digital MFI compensation algorithm is developed. The compensation performance is illustrated in practical single- and multiband reception scenarios, considering desired signal bandwidths up to 20 MHz. In the multiband scenario, allowing reception and detection of noncontiguous frequency channels with a single receiver chain, the digital compensation processing is done sub-bandwise, securing reliable functionality also under strongly frequency-selective interference. In the applied single- and multistage QΣΔM architectures, the I/Q mismatches are considered in all the QΣΔM branches as well as in the preceding receiver front-end, modeling the challenging and realistic scenario where the whole receiver chain includes cascaded in-phase/quadrature (I/Q) mismatch sources. As a whole, developing digital MFI compensation is a significant step towards practical receiver implementations with QΣΔM ADCs. In consequence, this allows the exploitation of the multiband and reconfigurability properties. The proposed design can be implemented without additional analog components and is straightforwardly reconfigurable in dynamic signal conditions typical for DSA and CR systems, e.g., in case of frequency hand-off because of a primary user appearance. In addition, the digital post-compensation of the MFI eases the strict demands for the matching of the analog circuits in SDRs

Concurrent Multi-Band Envelope Tracking Power Amplifiers for Emerging Wireless Communications

Emerging wireless communication is shifting toward data-centric broadband services, resulting in employment of sophisticated and spectrum efficient modulation and access techniques. This yields communication signals with large peak-to-average power ratios (PAPR) and stringent linearity requirements. For example, future wireless communication standard, such as long term evolution advanced (LTE-A) require adoption of carrier aggregation techniques to improve their effective modulation bandwidth. The carrier aggregation technique for LTE-A incorporates multiple carriers over a wide frequency range to create a wider bandwidth of up to 100MHz. This will require future power amplifiers (PAs) and transmitters to efficiently amplify concurrent multi-band signals with large PAPR, while maintaining good linearity. Different back-off efficiency enhancement techniques are available, such as envelope tracking (ET) and Doherty. ET has gained a lot of attention recently as it can be applied to both base station and mobile transmitters. Unfortunately, few publications have investigated concurrent multi-band amplification using ET PAs, mainly due to the limited bandwidth of the envelope amplifier. In this thesis, a novel approach to enable concurrent amplification of multi-band signals using a single ET PA will be presented. This thesis begins by studying the sources of nonlinearities in single-band and dual-band PAs. Based on the analysis, a design methodology is proposed to reduce the sources of memory effects in single-band and dual-band PAs from the circuit design stage and improve their linearizability. Using the proposed design methodology, a 45W GaN PA was designed. The PA was linearized using easy to implement, memoryless digital pre-distortion (DPD) with 8 and 28 coefficients when driven with single-band and dual-band signals, respectively. This analysis and design methodology will enable the design of PAs with reduced memory effects, which can be linearized using simple, power efficient linearization techniques, such as lookup table or memoryless polynomial DPD. Note that the power dissipation of the linearization engine becomes crucial as we move toward smaller base station cells, such as femto- and pico-cells, where complicated DPD models cannot be implemented due to their significant power overhead. This analysis is also very important when implementing a multi-band ET PA system, where the sources of memory effects in the PA itself are minimized through the proposed design methodology. Next, the principle of concurrent dual-band ET operation using the low frequency component (LFC) of the envelope of the dual-band signal is presented. The proposed dual-band ET PA modulates the drain voltage of the PA using the LFC of the envelope of the dual-band signal. This will enable concurrent dual-band operation of the ET PA without posing extra bandwidth requirements on the envelope amplifier. A detailed efficiency and linearity analysis of the dual-band ET PA is also presented. Furthermore, a new dual-band DPD model with supply dependency is proposed in this thesis, capable of capturing and compensating for the sources of distortion in the dual-band ET PA. To the best of our knowledge, concurrent dual-band operation of ET PAs using the LFC of the envelope of the dual-band signal is presented for the first time in the literature. The proposed dual-band ET operation is validated using the measurement results of two GaN ET PA prototypes. Lastly, the principle of concurrent dual-band ET operation is extended to multi-band signals using the LFC of the envelope of the multi-band signal. The proposed multi-band ET operation is validated using the measurement results of a tri-band ET PA. To the best of our knowledge, this is the first reported tri-band ET PA in literature. The tri-band ET PA is linearized using a new tri-band DPD model with supply dependency

Digital Signal Processing Techniques Applied to Radio over Fiber Systems

The dissertation aims to analyze different Radio over Fiber systems for the front-haul applications. Particularly, analog radio over fiber (A-RoF) are simplest and suffer from nonlinearities, therefore, mitigating such nonlinearities through digital predistortion are studied. In particular for the long haul A-RoF links, direct digital predistortion technique (DPDT) is proposed which can be applied to reduce the impairments of A-RoF systems due to the combined effects of frequency chirp of the laser source and chromatic dispersion of the optical channel. Then, indirect learning architecture (ILA) based structures namely memory polynomial (MP), generalized memory polynomial (GMP) and decomposed vector rotation (DVR) models are employed to perform adaptive digital predistortion with low complexities. Distributed feedback (DFB) laser and vertical capacity surface emitting lasers (VCSELs) in combination with single mode/multi-mode fibers have been linearized with different quadrature amplitude modulation (QAM) formats for single and multichannel cases. Finally, a feedback adaptive DPD compensation is proposed. Then, there is still a possibility to exploit the other realizations of RoF namely digital radio over fiber (D-RoF) system where signal is digitized and transmits the digitized bit streams via digital optical communication links. The proposed solution is robust and immune to nonlinearities up-to 70 km of link length. Lastly, in light of disadvantages coming from A-RoF and D-RoF, it is still possible to take only the advantages from both methods and implement a more recent form knows as Sigma Delta Radio over Fiber (S-DRoF) system. Second Order Sigma Delta Modulator and Multi-stAge-noise-SHaping (MASH) based Sigma Delta Modulator are proposed. The workbench has been evaluated for 20 MHz LTE signal with 256 QAM modulation. Finally, The 6x2 GSa/s sigma delta modulators are realized on FPGA to show a real time demonstration of S-DRoF system. The demonstration shows that S-DRoF is a competitive competitor for 5G sub-6GHz band applications

Frequency Synthesis in Wireless and Wireline Systems

First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2

Investigation of Orthogonal Frequency Division Multiplexing Based Power Line Communication Systems

Power Line Communication (PLC) has the potential to become the preferred technique for providing broadband to homes and offices with the advantage of eliminating the need for new wiring infrastructure and reducing the cost. Power line grids, however, present a hostile channel for data communication, since the fundamental purpose of the power line channel was only the transmission of electric power at 50/60 Hz frequencies. The development of PLC systems for providing broadband applications requires an adequate knowledge of the power line channel characteristics. Various types of noise and multipath effects are some of the limitations for power line channels which need to be considered carefully in designing PLC systems. An effect of an impulsive noise characterized with short durations is identified as one of the major impairment in PLC system. Orthogonal Frequency Division Multiplexing (OFDM) technique is one of the modulation approaches which has been regarded as the modulation technique for PLC systems by most researchers in the field and is used in this research study work. This is because it provides high robustness against impulsive noise and minimizes the effects of multipath. In case of impulsive noise affecting the OFDM system, this effect is spread over multiple subcarriers due to Discrete Fourier Transform (DFT) at the receiver. Hence, each of the transmitted communication symbols is only affected by a fraction of the impulsive noise. In order to achieve reliable results for data transmission, a proper power line channel with various noise models must be used in the investigations. In this research study work, a multipath model which has been widely accepted by many researchers in the field and practically proven in the Tanzanian power line system is used as the model for the power line channel. The effects of different scenarios such as variations in direct path length, path number, branch length and load on the channel frequency response are investigated in this research work. Simulation results indicate the suitability of multi-carrier modulation technique such as an OFDM over the power line channels. To represent the actual noise scenario in the power line channel, an impulsive noise and background noise are classified as the two main noise sources. A Middleton class A noise is modelled as an impulsive noise, whereas the background noise is modelled as an Additive White Gaussian Noise (AWGN). The performance of PLC system based on OFDM is investigated under Middleton Class A and AWGN noise scenarios. It is observed that Bit Error Rate (BER) for the impulsive noise is higher than the background noise. Since channel coding can enhance the transmission in a communication system, Block code and convolutional codes have been studied in this research work. The hamming code chosen as a type of the block code, whereas the Trellis Coded Modulation (TCM) selected from the category of the convolutional channel codes and modelled in Matlab2013b. Although TCM code produces improvements in the Signal-to-Noise Ratio (SNR), they do not perform well with Middleton class A noise. A rectangular 16-QAM TCM based on OFDM provides better BER rate compared to the general TCM

Low-power adaptive control scheme using switching activity measurement method for reconfigurable analog-to-digital converters

Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Recent Trends in Communication Networks

In recent years there has been many developments in communication technology. This has greatly enhanced the computing power of small handheld resource-constrained mobile devices. Different generations of communication technology have evolved. This had led to new research for communication of large volumes of data in different transmission media and the design of different communication protocols. Another direction of research concerns the secure and error-free communication between the sender and receiver despite the risk of the presence of an eavesdropper. For the communication requirement of a huge amount of multimedia streaming data, a lot of research has been carried out in the design of proper overlay networks. The book addresses new research techniques that have evolved to handle these challenges