Design, Analysis, and Simulation of a Jitter Reduction Circuit (JRC) System at 1GHz

The clock signal is considered as the “heartbeat” of a digital system yet jitter which is a variation on the arrival time of the clock edge, could undermine the overall performance or even cause failures on the system. Deterministic jitter could be reduced during the designing process however random jitter during operation is somehow less-controllable and unavoidable. Being able to remove jitter on the clock would therefore play a vital role in system performance improvement. This thesis implements a 1GHz fully feedforward jitter reduction circuit (JRC) which can be used as an on-chip IP core at clock tree terminals to provide a low jitter clock signal to a local clock network or be used at the clock insertion point to reduce jitter from an off chip signal. It can also be stand-alone and used on PCB designs to reduce jitter on the high-frequency clock signal used on the board. This jitter attenuation circuit is implemented using IBM CMHV7SF 180nm MOSFET process, demonstrates a jitter reduction of at least 8dB at 1GHz with 33ps rms Gaussian random jitter (for a 200ps peak-to-peak randomly changing rising edge input signal)

Bidirectional Neural Interface Circuits with On-Chip Stimulation Artifact Reduction Schemes

Bidirectional neural interfaces are tools designed to “communicate” with the brain via recording and modulation of neuronal activity. The bidirectional interface systems have been adopted for many applications. Neuroscientists employ them to map neuronal circuits through precise stimulation and recording. Medical doctors deploy them as adaptable medical devices which control therapeutic stimulation parameters based on monitoring real-time neural activity. Brain-machine-interface (BMI) researchers use neural interfaces to bypass the nervous system and directly control neuroprosthetics or brain-computer-interface (BCI) spellers. In bidirectional interfaces, the implantable transducers as well as the corresponding electronic circuits and systems face several challenges. A high channel count, low power consumption, and reduced system size are desirable for potential chronic deployment and wider applicability. Moreover, a neural interface designed for robust closed-loop operation requires the mitigation of stimulation artifacts which corrupt the recorded signals. This dissertation introduces several techniques targeting low power consumption, small size, and reduction of stimulation artifacts. These techniques are implemented for extracellular electrophysiological recording and two stimulation modalities: direct current stimulation for closed-loop control of seizure detection/quench and optical stimulation for optogenetic studies. While the two modalities differ in their mechanisms, hardware implementation, and applications, they share many crucial system-level challenges. The first method aims at solving the critical issue of stimulation artifacts saturating the preamplifier in the recording front-end. To prevent saturation, a novel mixed-signal stimulation artifact cancellation circuit is devised to subtract the artifact before amplification and maintain the standard input range of a power-hungry preamplifier. Additional novel techniques have been also implemented to lower the noise and power consumption. A common average referencing (CAR) front-end circuit eliminates the cross-channel common mode noise by averaging and subtracting it in analog domain. A range-adapting SAR ADC saves additional power by eliminating unnecessary conversion cycles when the input signal is small. Measurements of an integrated circuit (IC) prototype demonstrate the attenuation of stimulation artifacts by up to 42 dB and cross-channel noise suppression by up to 39.8 dB. The power consumption per channel is maintained at 330 nW, while the area per channel is only 0.17 mm2. The second system implements a compact headstage for closed-loop optogenetic stimulation and electrophysiological recording. This design targets a miniaturized form factor, high channel count, and high-precision stimulation control suitable for rodent in-vivo optogenetic studies. Monolithically integrated optoelectrodes (which include 12 µLEDs for optical stimulation and 12 electrical recording sites) are combined with an off-the-shelf recording IC and a custom-designed high-precision LED driver. 32 recording and 12 stimulation channels can be individually accessed and controlled on a small headstage with dimensions of 2.16 x 2.38 x 0.35 cm and mass of 1.9 g. A third system prototype improves the optogenetic headstage prototype by furthering system integration and improving power efficiency facilitating wireless operation. The custom application-specific integrated circuit (ASIC) combines recording and stimulation channels with a power management unit, allowing the system to be powered by an ultra-light Li-ion battery. Additionally, the µLED drivers include a high-resolution arbitrary waveform generation mode for shaping of µLED current pulses to preemptively reduce artifacts. A prototype IC occupies 7.66 mm2, consumes 3.04 mW under typical operating conditions, and the optical pulse shaping scheme can attenuate stimulation artifacts by up to 3x with a Gaussian-rise pulse rise time under 1 ms.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147674/1/mendrela_1.pd

Transformerless Microinverter with Low Leakage Current Circulation and Low Input Capacitance Requirement for PV Applications

The inevitable depletion of limited fossil fuels combined with their harmful footprint on the environment led to a global pursuit for alternative energy sources that are clean and inexhaustible. Renewable energies such as wind, biomass and solar are the best alternative energy candidates, with the latter being more suitable for GCC countries. Besides, the energy generated from photovoltaic (PV) modules is one of the elegant examples of harnessing solar energy, as it is clean, pollutant-free and modular. Furthermore, recent advances in PV technology, especially grid-connected PV systems revealed the preeminence of using multiple small inverters called (Microinverters) over using the conventional single inverter configuration. Specifically, the break-even cost point can be reached faster and the system modularity increases with microinverters usage. Nonetheless, due to microinverter’s small ratings designers prefer transformerless designs because transformer removal achieves higher efficiency and power density. However, the transformer removal results in loss of galvanic isolation that leads to dangerous leakage current circulation that affects system safety. Another issue with microinverters is that since they are installed outside their bulky DC-Link electrolytic capacitor lifetime deteriorates the system reliability because electrolytic capacitor failure rate increases as temperature increases. Moreover, the DC-Link capacitor is used to decouple the 2nd order power harmonic ripples that appear in single-phase systems. Thus, the objective of this thesis is to design an efficient transformerless microinverter that has low leakage current circulation and low input capacitance requirement with a minimum number of active switches. In other words, the objective is to increase the safety and the reliability of the system while maintaining the high efficiency. Eventually, the configuration selected is the transformerless differential buck microinverter with LCL filter and it is modeled with passive resonance damping and active resonance damping control

Time-Offset Fractional-N PLLs for Heterodyne FMCW SAR

This text contains an investigation into the use of time-offset fractional-N phase locked loops (PLLs) for heterodyne frequency-modulated continuous-wave (FMCW) synthetic aperture radar (SAR) and the impact of spurii on such a system. Heterodyne receiver architectures avoid phenomena which limit the sensitivity of their homodyne counterparts, and enable certain inter-antenna feed-through suppression techniques. Despite these advantages, homodyne receivers are more prevalent owing to advantages in size, weight and cost. Designed to address this dilemma, the miloSAR is believed to be the only heterodyne FMCW SAR to employ a pair of time-offset fractional-N PLLs for waveform synthesis to enable low-cost heterodyning and simplify filter-based feed-through suppression. This system architecture is revealed to be susceptible to swept-offset spurii termed spur chirps which hinder the sensor's performance. While integer boundary spurs and phase detector harmonics infamously plague fractional-N PLLs, their resultant spur-chirps have not seen analysis in the context of FMCW SAR. Simulations and measurements reveal that these spurii significantly degrade SAR image quality in terms of peak sidelobe ratio, structural similarity index measure and root mean square error. To combat this, several suppression techniques were assessed, namely: time domain zeroing, PLL loop bandwidth reduction, and a novel method termed range-Doppler spur masking. A subset of these suppression techniques were applied to measured SAR data sets, including car-borne data measured in Iowa, USA and airborne data captured in Oudtshoorn, South Africa. These results show that the impact of spur chirps can be effectively quelled, meaning that time-offset fractional-N PLLs offer an attractive, low-cost approach to the implementation of heterodyne FMCW SAR

Optical code-division multiple access system and optical signal processing

This thesis presents our recent researches on the development of coding devices, the investigation of security and the design of systems in the optical cod-division multiple access (OCDMA) systems. Besides, the techniques of nonlinear signal processing used in the OCDMA systems fire our imagination, thus some researches on all-optical signal processing are carried out and also summarized in this thesis. Two fiber Bragg grating (FBG) based coding devices are proposed. The first coding device is a superstructured FBG (SSFBG) using ±π/2-phase shifts instead of conventional 0/π-phase shifts. The ±π/2-phase-shifted SSFBG en/decoders can not only conceal optical codes well in the encoded signals but also realize the reutilization of available codes by hybrid use with conventional 0/π-phase-shifted SSFBG en/decoders. The second FBG based coding device is synthesized by layer-peeling method, which can be used for simultaneous optical code recognition and chromatic dispersion compensation. Then, two eavesdropping schemes, one-bit delay interference detection and differential detection, are demonstrated to reveal the security vulnerability of differential phase-shift keying (DPSK) and code-shift keying (CSK) OCDMA systems. To address the security issue as well as increase the transmission capacity, an orthogonal modulation format based on DPSK and CSK is introduced into the OCDMA systems. A 2 bit/symbol 10 Gsymbol/s transmission system using the orthogonal modulation format is achieved. The security of the system can be partially guaranteed. Furthermore, a fully-asynchronous gigabit-symmetric OCDMA passive optical network (PON) is proposed, in which a self-clocked time gate is employed for signal regeneration. A remodulation scheme is used in the PON, which let downstream and upstream share the same optical carrier, allowing optical network units source-free. An error-free 4-user 10 Gbit/s/user duplex transmission over 50 km distance is reazlied. A versatile waveform generation scheme is then studied. A theoretical model is established and a waveform prediction algorithm is summarized. In the demonstration, various waveforms are generated including short pulse, trapezoidal, triangular and sawtooth waveforms and doublet pulse. ii In addition, an all-optical simultaneous half-addition and half-subtraction scheme is achieved at an operating rate of 10 GHz by using only two semiconductor optical amplifiers (SOA) without any assist light. Lastly, two modulation format conversion schemes are demonstrated. The first conversion is from NRZ-OOK to PSK-Manchester coding format using a SOA based Mach-Zehnder interferometer. The second conversion is from RZ-DQPSK to RZ-OOK by employing a supercontinuum based optical thresholder

Dynamic modeling of pwm and single-switch single-stage power factor correction converters

The concept of averaging has been used extensively in the modeling of power electronic circuits to overcome their inherent time-variant nature. Among various methods, the PWM switch modeling approach is most widely accepted in the study of closed-loop stability and transient response because of its accuracy and simplicity. However, a non-ideal PWM switch model considering conduction losses is not available except for converters operating in continuous conduction mode (CCM) and under small ripple conditions. Modeling of conductor losses under large ripple conditions has not been reported in the open literature, especially when the converter operates in discontinuous conduction mode (DCM). In this dissertation, new models are developed to include conduction losses in the non-ideal PWM switch model under CCM and DCM conditions. The developed model is verified through two converter examples and the effect of conduction losses on the steady state and dynamic responses of the converter is also studied. Another major constraint of the PWM switch modeling approach is that it heavily relies on finding the three-terminal PWM switch. This requirement severely limits its application in modeling single-switch single-stage power factor correction (PFC) converters, where more complex topological structures and switching actions are often encountered. In this work, we developed a new modeling approach which extends the PWM switch concept by identifying the charging and discharging voltages applied to the inductors. The new method can be easily applied to derive large-signal models for a large group of PFC converters and the procedure is elaborated through a specific example. Finally, analytical results regarding harmonic contents and power factors of various PWM converters in PFC applications are also presented here

Hybrid receiver study

The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions

Power Converters in Power Electronics

In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters

Control of switched reluctance machines

This thesis is concerned with the control of switched reluctance machines for both motoring and generating applications. There are different control objectives in each case. For motoring operation, there are two possible control objectives. If the SRM is being employed in a servo-type application, the desire is for a constant output torque. However, for low performance applications where some amount of torque ripple is acceptable, the aim is to achieve efficient and accurate speed regulation. When the SRM is employed for generating purposes, the goal is to maintain the dc bus voltage at the required value while achieving maximum efficiency. Preliminary investigative work on switched reluctance machine control in both motoring and generating modes is performed. This includes the implementation and testing through simulation of two control strategies described in the literature. In addition, an experimental system is built for the development and testing of new control strategies. The inherent nonlinearity of the switched reluctance machine results in ripple in the torque profile. This adversely affects motoring performance for servo-type applications. Hence, three neuro-fuzzy control strategies for torque ripple minimisation in switched reluctance motors are developed. For all three control strategies, the training of a neurofuzzy compensator and the incorporation of the trained compensator into the overall switched reluctance drive are described. The performance of the control strategies in reducing the torque ripple is examined with simulations and through experimental testing. While the torque ripple is troublesome for servo-type applications, there are some applications where a certain amount of torque ripple is acceptable. Therefore, four simple motor control strategies for torque ripple-tolerant applications are described and tested experimentally. Three of the control strategies are for low speed motoring operation while the fourth is aimed at high speed motoring operation. Finally, three closed-loop generator control strategies aimed at high speed operation in single pulse mode are developed. The three control strategies are examined by testing on the experimental system. A comparison of the performance of the control strategies in terms of efficiency and peak current produced by each is presented