Software Defined Radio Implementation of Carrier and Timing Synchronization for Distributed Arrays

The communication range of wireless networks can be greatly improved by using distributed beamforming from a set of independent radio nodes. One of the key challenges in establishing a beamformed communication link from separate radios is achieving carrier frequency and sample timing synchronization. This paper describes an implementation that addresses both carrier frequency and sample timing synchronization simultaneously using RF signaling between designated master and slave nodes. By using a pilot signal transmitted by the master node, each slave estimates and tracks the frequency and timing offset and digitally compensates for them. A real-time implementation of the proposed system was developed in GNU Radio and tested with Ettus USRP N210 software defined radios. The measurements show that the distributed array can reach a residual frequency error of 5 Hz and a residual timing offset of 1/16 the sample duration for 70 percent of the time. This performance enables distributed beamforming for range extension applications.Comment: Submitted to 2019 IEEE Aerospace Conferenc

Robust Sampling Clock Recovery Algorithm for Wideband Networking Waveform of SDR

A novel technique for sampling clock recovery in a wideband networking waveform of a software defined radio is proposed. Sampling clock recovery is very important in wideband networking radio operation as it directly affects the Medium Access adaptive time slot switching rate. The proposed Sampling clock recovery algorithm consists of three stages. In the first stage, Sampling Clock Offset (SCO) is estimated at chip level. In the second stage, the SCO estimates are post-filtered to improve the tracking performance. We present a new post-filtering method namely Steady-State State-Space Recursive Least Squares with Adaptive Memory (S4RLSWAM). For the third stage of SCO compensation, a feedforward Lagrange interpolation based algorithm is proposed. Real-time hardware results have been presented to demonstrate the effectiveness of the proposed algorithms and architecture for systems requiring high data throughput. It is shown that both the proposed algorithms achieve better performance as compared to existing algorithms

Development of a Nanosatellite Software Defined Radio Communications System

Communications systems designed with application-specific integrated circuit (ASIC) technology suffer from one very significant disadvantage - the integrated circuits do not possess the ability of programmability. However, Software Defined Radio’s (SDR’s) integrated with Field Programmable Gate Arrays (FPGA) provide an opportunity to update the communication system on nanosatellites (which are physically difficult to access) due to their capability of performing signal processing in software. SDR signal processing is performed in software on reprogrammable elements such as FPGA’s. Applying this technique to nanosatellite communications systems will optimize the operations of the hardware, and increase the flexibility of the system. In this research a transceiver algorithm for a nanosatellite software defined radio communications is designed. The developed design is capable of modulation of data to transmit information and demodulation of data to receive information. The transceiver algorithm also works at different baud rates. The design implementation was successfully tested with FPGA-based hardware to demonstrate feasibility of the transceiver design with a hardware platform suitable for SDR implementation

Software-defined radio using LabVIEW and the PC sound card: A teaching platform for digital communications

Different modulation techniques and protocols require a standard communications laboratory for engineering courses to be equipped with a broad set of equipment, tools and accessories. However, the high costs involved in a hardware-based laboratory can become prohibitively expensive for many institutions. Software simulations alone can replicate most real-world applications with much lower costs. Nevertheless, they do not replace the real-world feeling provided by hardware-based systems, which can produce and receive physical signals to and from the exterior media. Advances in computer technology are allowing software-defined radio (SDR) concepts to be applied in many areas of communications. In this type of system, the baseband processing is performed completely in software while an analog RF front end hardware can be used for RF processing. The use of a software-defined radio platform in a digital communications laboratory can offer the benefits of software simulations coupled with the enthusiasm presented by hardware-based systems. A low-cost software-defined radio teaching platform implemented in LabVIEW using the personal computer sound card was developed for a digital communications laboratory along with a set of exercises to help students assimilate the concepts involved in communications theory and system implementation. This system allows for the generation, reception, processing, and analysis of signals in a 4 QAM (quadrature amplitude modulation) transceiver using the personal computer sound card to transmit and receive modulated signals. This teaching platform provides the means necessary to explore the theoretical concepts of digital communication systems in a laboratory environment. National Instruments\u27 LabVIEW graphical programming environment allows a more intuitive way of coding, which helps students to spend more time learning the relevant theory concepts and less time coding the applications. Being a flexible and modular system, modifications can be made for optimization and use with different and/or more complex techniques

Portable Waveform Development for Software Defined Radios

This work focuses on the question: "How can we build waveforms that can be moved from one platform to another?\u27\u27 Therefore an approach based on the Model Driven Architecture was evaluated. Furthermore, a proof of concept is given with the port of a TETRA waveform from a USRP platform to an SFF SDR platform

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation

Design and FPGA implementation of a SISO and a MIMO wireless system for software defined radio

MIMO (Multiple-input Multiple-output) technology combined with space time coding techniques provides significant increase in performance and capacity over an equivalent SISO (Single-input Single-output) system while maintaining the same bandwidth and transmission power. MIMO has emerged as the major breakthrough in recent communication technologies. To migrate from SISO to MIMO system, multiple RF (Radio Frequency) front ends and additional signal processing are required. Software defined radio (SDR) allows MIMO and other evolving techniques to be added to current systems through software update instead of hardware replacement. SDR provides a flexible and economic solution to the system upgrade and migration. In this thesis, an SDR based SISO system using QPSK modulation scheme is implemented on FPGA. The system produces signal with an intermediate frequency of 25 MHz and throughput of 12.5 Mbps. One carrier recovery and two symbol timing recovery algorithms (Gardner and Maximum Likelihood) are investigated and implemented. A 2x1 MIMO system using Alamouti scheme and CORDIC based carrier recovery is designed as well. The SDR based SISO system can be easily incorporated to the MIMO design. Throughout this thesis, detailed design information is presented along with both computer simulation results and real hardware performance. The comparisons of different algorithms and component structures are also provided. Based on these comparisons, the suitable algorithm or structure according to specific implementation considerations and system requirement can be selected. The design and implementation are processed based on a system-level design flow. System modeling and simulation are performed using Xilinx's System Generator for DSP and Simulink. After it is mapped to HDL (Hardware Description Language) netlist, the design is synthesized and implemented by Xilinx's ISE tool. The generated bit-stream is then downloaded to target FPGA to program the device. The hardware performance is measured by BER (Bit Error Rate) tester, oscilloscope and spectrum analyzer. This thesis is an initial project for future work of Wireless Design Laboratory at Concordia University. The system realized in this project can be viewed as a base of future MIMO implementation with different number of antennas and advanced signal processing techniques

COGNITIVE RADIO SOLUTION FOR IEEE 802.22

Current wireless systems suffer severe radio spectrum underutilization due to a number of problematic issues, including wasteful static spectrum allocations; fixed radio functionalities and architectures; and limited cooperation between network nodes. A significant number of research efforts aim to find alternative solutions to improve spectrum utilization. Cognitive radio based on software radio technology is one such novel approach, and the impending IEEE 802.22 air interface standard is the first based on such an approach. This standard aims to provide wireless services in wireless regional area network using TV spectrum white spaces. The cognitive radio devices employed feature two fundamental capabilities, namely supporting multiple modulations and data-rates based on wireless channel conditions and sensing a wireless spectrum. Spectrum sensing is a critical functionality with high computational complexity. Although the standard does not specify a spectrum sensing method, the sensing operation has inherent timing and accuracy constraints.This work proposes a framework for developing a cognitive radio system based on a small form factor software radio platform with limited memory resources and processing capabilities. The cognitive radio systems feature adaptive behavior based on wireless channel conditions and are compliant with the IEEE 802.22 sensing constraints. The resource limitations on implementation platforms post a variety of challenges to transceiver configurability and spectrum sensing. Overcoming these fundamental features on small form factors paves the way for portable cognitive radio devices and extends the range of cognitive radio applications.Several techniques are proposed to overcome resource limitation on a small form factor software radio platform based on a hybrid processing architecture comprised of a digital signal processor and a field programmable gate array. Hardware reuse and task partitioning over a number of processing devices are among the techniques used to realize a configurable radio transceiver that supports several communication modes, including modulations and data rates. In particular, these techniques are applied to build configurable modulation architecture and a configurable synchronization. A mode-switching architecture based on circular buffers is proposed to facilitate a reliable transitioning between different communication modes.The feasibility of efficient spectrum sensing based on a compressive sampling technique called "Fast Fourier Sampling" is examined. The configuration parameters are analyzed mathematically, and performance is evaluated using computer simulations for local spectrum sensing applications. The work proposed herein features a cooperative Fast Fourier sampling scheme to extend the narrowband and wideband sensing performance of this compressive sensing technique.The précis of this dissertation establishes the foundation of efficient cognitive radio implementation on small form factor software radio of hybrid processing architecture