Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

Glitch Control with Dynamic Receiver Threshold Adjustment

A novel method to treat crosstalk induced glitches on local interconnects is presented. Design irregularities and manufacturing defects in system-on-chip interconnects may result in spurious electrical events that impact the reliability of the interconnect infrastructure. Conventional repeater insertion methods prove to be space and power demanding. The proposed method acts by dynamically adjusting the threshold voltage of the receiving gate without breaking the line in multiple segments. A comparative study is presented that supports the applicability of the approach

Study to develop process controls for line certification on hybrid microcircuits Final report, Nov. 1970 - Feb. 1971

Basic process steps for fabrication of thick or thin film microcircuits for NASA us

Microwave Reflectometry for Physical Inspections

Utilizing microwave reflections to compare a reference device with counterfeit and/or aging devices under test. The reflection from the device under test varies based on certain properties, which results in each device having a unique and intrinsic electromagnetic signature. Comparisons of the electromagnetic signature of the device under test to the electromagnetic signature of a reference device enable evaluating the acceptability of the device under test

Electrical characterization of plasma-enhanced Cvd silicon nitride dielectric on copper

In this work, a novel metal-insulator-metal (MIM) capacitor process is introduced and integrated in a Copper Interconnect technology, whose smallest feature size is 0.18mum process, which has good yield, reliability and repeatability. The MIM uses a one-photomask process and hence is termed as the Low-cost-integration (LCI) MIM. The LCI MIM uses copper as the bottom electrode, plasma enhanced silicon nitride as the dielectric, and Tantalum nitride as the top electrode. The target capacitance density is 1.5fF/mum2. The target leakage current is 1e-7A/cm2 at 3.3V at 125°C. The maximum operating voltages that the MIM is designed for is 5V. The voltage linearity is desired to be less than 100ppm/v; The purpose of the study is to determine the feasibility of integrating the low-cost-integration (LCI) MIM capacitor and to characterize the device to ensure that it meets the above mentioned target values for the various parameters. This is done by electrically characterizing the capacitor for the capacitance change with voltage, the leakage current at accelerated voltages and the time-dependent-dielectric breakdown (TDDB) under various electric fields. (Abstract shortened by UMI.)

On the deployment of on-chip noise sensors

The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the issue, recently several works have shed light on the possibilities of dynamic noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume that the placement of the sensors is given. It remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection. The problem of noise sensor placement is defined at first along with a novel sensing quality metric (SQM) to be maximized. The threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and false alarms. The problem of minimizing the system alarm rate subject to a given system failure rate constraint is formulated. It is further shown that with the help of IDDQ measurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. In the third chapter, a novel framework to predict the resonance frequency using existing on-chip noise sensors, based on the theory of 1-bit compressed sensing is proposed. The proposed framework can help to achieve the resonance frequency of individual chips so as to effectively avoid resonance noise at runtime --Abstract, page iii

Demonstration of High-Temperature Operation of Beta-Gallium Oxide (β-Ga2O3) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) with Electrostatic Model in COMSOL

β-Ga2O3 is a robust semiconductor material set with a large band gap of ~4.8 eV, low intrinsic carrier concentration, and high melting point that offers a stable platform for operating electronic devices at high temperatures and extreme environments. The first half of this thesis will cover the fabrication of a fixture and packaging to test electronic components at high temperatures. Then it will highlight the characterization of β-Ga2O3 field effect transistors from room temperature (RT) up to 500 °C. The devices, fabricated with Ni/Au and Al2O3 gate metal-oxide-semiconductor (MOS), demonstrate stable operation up to 500 oC. The tested device shows no measured current degradation in the ID-VD characteristics up to 450 oC. Improvements to the drain current, ID within this temperature range are due to activation carriers from dopants/traps and the negative push in threshold voltage, VT. The device exhibits a drop in ID at 500 °C; however, device characteristics recover once the device returns to RT. Even after 20 hours of device operation at 500 °C, the device shows negligible degradation. Device characteristics such as gate leakage, ION/IOFF ratio, gm, Ron, and contact resistance show monotonic variation with temperature. The experimental results suggest that an optimized choice of metals and gate dielectrics β-Ga2O3 will provide a platform for device operation at high temperatures and extreme environments. The second half of the thesis focuses on creating an electrostatic model of a metal-oxide-semiconductor field effect transistor with COMSOL finite element analysis software to understand the physics behind semiconductor technology