Principles, fundamentals, and applications of programmable integrated photonics

[EN] Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore¿s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach¿Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.European Research Council; Conselleria d'Educació, Investigació, Cultura i Esport; Ministerio de Ciencia, Innovación y Universidades; European Cooperation in Science and Technology; Horizon 2020 Framework Programme.Pérez-López, D.; Gasulla Mestre, I.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Principles, fundamentals, and applications of programmable integrated photonics. Advances in Optics and Photonics. 12(3):709-786. https://doi.org/10.1364/AOP.387155709786123Lyke, J. C., Christodoulou, C. G., Vera, G. A., & Edwards, A. H. (2015). An Introduction to Reconfigurable Systems. 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Integrated Microwave Photonic Processors using Waveguide Mesh Cores

Integrated microwave photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint and cost. Application Specific Photonic Integrated Circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long-development times and costly implementations. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable Microwave Photonic processor, where a common hardware implemented by the combination of microwave, photonic and electronic subsystems, realizes different functionalities through programming. Here, we propose the first-ever generic-purpose Microwave Photonic processor concept and architecture. This versatile processor requires a powerful end-to-end field-based analytical model to optimally configure all their subsystems as well as to evaluate their performance in terms of the radiofrequency gain, noise and dynamic range. Therefore, we develop a generic model for integrated Microwave Photonics systems. The key element of the processor is the reconfigurable optical core. It requires high flexibility and versatility to enable reconfigurable interconnections between subsystems as well as the synthesis of photonic integrated circuits. For this element, we focus on a 2-dimensional photonic waveguide mesh based on the interconnection of tunable couplers. Within the framework of this Thesis, we have proposed two novel interconnection schemes, aiming for a mesh design with a high level of versatility. Focusing on the hexagonal waveguide mesh, we explore the synthesis of a high variety of photonic integrated circuits and particular Microwave Photonics applications that can potentially be performed on a single hardware. In addition, we report the first-ever demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate a world-record number of functionalities on a single photonic integrated circuit enabling over 30 different functionalities from the 100 that could be potentially obtained with a simple seven hexagonal cell structure. The resulting device can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks as well as quantum information systems. Our work is an important step towards this paradigm and sets the base for a new era of generic-purpose photonic integrated systems.Los dispositivos integrados de fotónica de microondas ofrecen soluciones optimizadas para los sistemas de información y comunicación. Generalmente, están compuestos por diferentes arquitecturas en las que subsistemas ópticos y electrónicos se integran para optimizar las prestaciones, el consumo, el tamaño y el coste del dispositivo final. Hasta ahora, los circuitos/chips de propósito específico se han diseñado para proporcionar una funcionalidad concreta, requiriendo así un número considerable de iteraciones entre las etapas de diseño, fabricación y medida, que origina tiempos de desarrollo largos y costes demasiado elevados. Una alternativa, inspirada por las FPGA (del inglés Field Programmable Gate Array), es el procesador fotónico programable. Este dispositivo combina la integración de subsistemas de microondas, ópticos y electrónicos para realizar, mediante la programación de los mismos y sus interconexiones, diferentes funcionalidades. En este trabajo, proponemos por primera vez el concepto del procesador de propósito general, así como su arquitectura. Además, con el fin de diseñar, optimizar y evaluar las prestaciones básicas del dispositivo, hemos desarrollado un modelo analítico extremo a extremo basado en las componentes del campo electromagnético. El modelo desarrollado proporciona como resultado la ganancia, el ruido y el rango dinámico global para distintas configuraciones de modulación y detección, en función de los subsistemas y su configuración. El elemento principal del procesador es su núcleo óptico reconfigurable. Éste requiere un alto grado de flexibilidad y versatilidad para reconfigurar las interconexiones entre los distintos subsistemas y para sintetizar los circuitos para el procesado óptico. Para este subsistema, proponemos el diseño de guías de onda reconfigurables para la creación de mallados bidimensionales. En el marco de esta tesis, hemos propuesto dos nuevos nodos de interconexión óptica para mallas reconfigurables, con el objetivo de obtener un mayor grado de versatilidad. Una vez escogida la malla hexagonal para el núcleo del procesador, hemos analizado la configuración de un gran número de circuitos fotónicos integrados y de funcionalidades de fotónica de microondas. El trabajo se ha completado con la demonstración de la primera malla reconfigurable integrada en un chip de silicio, demostrando además la síntesis de 30 de las 100 funcionalidades que potencialmente se pueden obtener con la malla diseñada compuesta de 7 celdas hexagonales. Este hecho supone un record frente a los sistemas de propósito específico. El sistema puede aplicarse en diferentes campos como las comunicaciones, los sensores químicos y biomédicos, el procesado de señales, la gestión y procesamiento de redes y los sistemas de información cuánticos. El conjunto del trabajo realizado representa un paso importante en la evolución de este paradigma, y sienta las bases para una nueva era de dispositivos fotónicos de propósito general.Els dispositius integrats de Fotònica de Microones oferixen solucions optimitzades per als sistemes d'informació i comunicació. Generalment, estan compostos per diferents arquitectures en què subsistemes òptics i electrònics s'integren per a optimitzar les prestacions, el consum, la grandària i el cost del dispositiu final. Fins ara, els circuits/xips de propòsit específic s'han dissenyat per a proporcionar una funcionalitat concreta, requerint així un nombre considerable d'iteracions entre les etapes de disseny, fabricació i mesura, que origina temps de desenrotllament llargs i costos massa elevats. Una alternativa, inspirada per les FPGA (de l'anglés Field Programmable Gate Array), és el processador fotònic programable. Este dispositiu combina la integració de subsistemes de microones, òptics i electrònics per a realitzar, per mitjà de la programació dels mateixos i les seues interconnexions, diferents funcionalitats. En este treball proposem per primera vegada el concepte del processador de propòsit general, així com la seua arquitectura. A més, a fi de dissenyar, optimitzar i avaluar les prestacions bàsiques del dispositiu, hem desenrotllat un model analític extrem a extrem basat en els components del camp electromagnètic. El model desenrotllat proporciona com resultat el guany, el soroll i el rang dinàmic global per a distintes configuracions de modulació i detecció, en funció dels subsistemes i la seua configuració. L'element principal del processador és el seu nucli òptic reconfigurable. Este requerix un alt grau de flexibilitat i versatilitat per a reconfigurar les interconnexions entre els distints subsistemes i per a sintetitzar els circuits per al processat òptic. Per a este subsistema, proposem el disseny de guies d'onda reconfigurables per a la creació de mallats bidimensionals. En el marc d'esta tesi, hem proposat dos nous nodes d'interconnexió òptica per a malles reconfigurables, amb l'objectiu d'obtindre un major grau de versatilitat. Una vegada triada la malla hexagonal per al nucli del processador, hem analitzat la configuració d'un gran nombre de circuits fotónicos integrats i de funcionalitats de fotónica de microones. El treball s'ha completat amb la demostració de la primera malla reconfigurable integrada en un xip de silici, demostrant a més la síntesi de 30 de les 100 funcionalitats que potencialment es poden obtindre amb la malla dissenyada composta de 7 cèl·lules hexagonals. Este fet suposa un rècord enfront dels sistemes de propòsit específic. El sistema pot aplicarse en diferents camps com les comunicacions, els sensors químics i biomèdics, el processat de senyals, la gestió i processament de xarxes i els sistemes d'informació quàntics. El conjunt del treball realitzat representa un pas important en l'evolució d'este paradigma, i assenta les bases per a una nova era de dispositius fotónicos de propòsit general.Pérez López, D. (2017). Integrated Microwave Photonic Processors using Waveguide Mesh Cores [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/91232TESI

Efficient parallel processing with optical interconnections

With the advances in VLSI technology, it is now possible to build chips which can each contain thousands of processors. The efficiency of such chips in executing parallel algorithms heavily depends on the interconnection topology of the processors. It is not possible to build a fully interconnected network of processors with constant fan-in/fan-out using electrical interconnections. Free space optics is a remedy to this limitation. Qualities exclusive to the optical medium are its ability to be directed for propagation in free space and the property that optical channels can cross in space without any interference. In this thesis, we present an electro-optical interconnected architecture named Optical Reconfigurable Mesh (ORM). It is based on an existing optical model of computation. There are two layers in the architecture. The processing layer is a reconfigurable mesh and the deflecting layer contains optical devices to deflect light beams. ORM provides three types of communication mechanisms. The first is for arbitrary planar connections among sets of locally connected processors using the reconfigurable mesh. The second is for arbitrary connections among N of the processors using the electrical buses on the processing layer and N2 fixed passive deflecting units on the deflection layer. The third is for arbitrary connections among any of the N2 processors using the N2 mechanically reconfigurable deflectors in the deflection layer. The third type of communication mechanisms is significantly slower than the other two. Therefore, it is desirable to avoid reconfiguring this type of communication during the execution of the algorithms. Instead, the optical reconfiguration can be done before the execution of each algorithm begins. Determining a right configuration that would be suitable for the entire configuration of a task execution is studied in this thesis. The basic data movements for each of the mechanisms are studied. Finally, to show the power of ORM, we use all three types of communication mechanisms in the first O(logN) time algorithm for finding the convex hulls of all figures in an N x N binary image presented in this thesis

Center for Aeronautics and Space Information Sciences

This report summarizes the research done during 1991/92 under the Center for Aeronautics and Space Information Science (CASIS) program. The topics covered are computer architecture, networking, and neural nets

Flexible LDPC Decoder Architectures

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption

Parallel Architectures for Planetary Exploration Requirements (PAPER)

The Parallel Architectures for Planetary Exploration Requirements (PAPER) project is essentially research oriented towards technology insertion issues for NASA's unmanned planetary probes. It was initiated to complement and augment the long-term efforts for space exploration with particular reference to NASA/LaRC's (NASA Langley Research Center) research needs for planetary exploration missions of the mid and late 1990s. The requirements for space missions as given in the somewhat dated Advanced Information Processing Systems (AIPS) requirements document are contrasted with the new requirements from JPL/Caltech involving sensor data capture and scene analysis. It is shown that more stringent requirements have arisen as a result of technological advancements. Two possible architectures, the AIPS Proof of Concept (POC) configuration and the MAX Fault-tolerant dataflow multiprocessor, were evaluated. The main observation was that the AIPS design is biased towards fault tolerance and may not be an ideal architecture for planetary and deep space probes due to high cost and complexity. The MAX concepts appears to be a promising candidate, except that more detailed information is required. The feasibility for adding neural computation capability to this architecture needs to be studied. Key impact issues for architectural design of computing systems meant for planetary missions were also identified

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.Siirretty Doriast

Parallel Architectures and Parallel Algorithms for Integrated Vision Systems

Computer vision is regarded as one of the most complex and computationally intensive problems. An integrated vision system (IVS) is a system that uses vision algorithms from all levels of processing to perform for a high level application (e.g., object recognition). An IVS normally involves algorithms from low level, intermediate level, and high level vision. Designing parallel architectures for vision systems is of tremendous interest to researchers. Several issues are addressed in parallel architectures and parallel algorithms for integrated vision systems