276 research outputs found
Subword complexity and Laurent series with coefficients in a finite field
Decimal expansions of classical constants such as , and
have long been a source of difficult questions. In the case of
Laurent series with coefficients in a finite field, where no carry-over
difficulties appear, the situation seems to be simplified and drastically
different. On the other hand, Carlitz introduced analogs of real numbers such
as , or . Hence, it became reasonable to enquire how
"complex" the Laurent representation of these "numbers" is. In this paper we
prove that the inverse of Carlitz's analog of , , has in general a
linear complexity, except in the case , when the complexity is quadratic.
In particular, this implies the transcendence of over \F_2(T). In the
second part, we consider the classes of Laurent series of at most polynomial
complexity and of zero entropy. We show that these satisfy some nice closure
properties
Integration and conjugacy in knot theory
This thesis consists of three self-contained chapters. The first two concern
quantum invariants of links and three manifolds and the third contains results
on the word problem for link groups.
In chapter 1 we relate the tree part of the Aarhus integral to the
mu-invariants of string-links in homology balls thus generalizing results of
Habegger and Masbaum.
There is a folklore result in physics saying that the Feynman integration of
an exponential is itself an exponential. In chapter 2 we state and prove an
exact formulation of this statement in the language which is used in the theory
of finite type invariants.
The final chapter is concerned with properties of link groups. In particular
we study the relationship between known solutions from small cancellation
theory and normal surface theory for the word and conjugacy problems of the
groups of (prime) alternating links. We show that two of the algorithms in the
literature for solving the word problem, each using one of the two approaches,
are the same. Then, by considering small cancellation methods, we give a normal
surface solution to the conjugacy problem of these link groups and characterize
the conjugacy classes. Finally as an application of the small cancellation
properties of link groups we give a new proof that alternating links are
non-trivial.Comment: University of Warwick Ph.D. thesi
Apollonian Circle Packings: Geometry and Group Theory III. Higher Dimensions
This paper gives -dimensional analogues of the Apollonian circle packings
in parts I and II. We work in the space \sM_{\dd}^n of all -dimensional
oriented Descartes configurations parametrized in a coordinate system,
ACC-coordinates, as those real matrices \bW with \bW^T
\bQ_{D,n} \bW = \bQ_{W,n} where is the -dimensional Descartes quadratic
form, , and \bQ_{D,n} and
\bQ_{W,n} are their corresponding symmetric matrices. There are natural
actions on the parameter space \sM_{\dd}^n. We introduce -dimensional
analogues of the Apollonian group, the dual Apollonian group and the
super-Apollonian group. These are finitely generated groups with the following
integrality properties: the dual Apollonian group consists of integral matrices
in all dimensions, while the other two consist of rational matrices, with
denominators having prime divisors drawn from a finite set depending on the
dimension. We show that the the Apollonian group and the dual Apollonian group
are finitely presented, and are Coxeter groups. We define an Apollonian cluster
ensemble to be any orbit under the Apollonian group, with similar notions for
the other two groups. We determine in which dimensions one can find rational
Apollonian cluster ensembles (all curvatures rational) and strongly rational
Apollonian sphere ensembles (all ACC-coordinates rational).Comment: 37 pages. The third in a series on Apollonian circle packings
beginning with math.MG/0010298. Revised and extended. Added: Apollonian
groups and Apollonian Cluster Ensembles (Section 4),and Presentation for
n-dimensional Apollonian Group (Section 5). Slight revision on March 10, 200
A Solder-Defined Computer Architecture for Backdoor and Malware Resistance
This research is about securing control of those devices we most depend on for integrity and confidentiality. An emerging concern is that complex integrated circuits may be subject to exploitable defects or backdoors, and measures for inspection and audit of these chips are neither supported nor scalable. One approach for providing a “supply chain firewall” may be to forgo such components, and instead to build central processing units (CPUs) and other complex logic from simple, generic parts. This work investigates the capability and speed ceiling when open-source hardware methodologies are fused with maker-scale assembly tools and visible-scale final inspection. The author has designed, and demonstrated in simulation, a 36-bit CPU and protected memory subsystem that use only synchronous static random access memory (SRAM) and trivial glue logic integrated circuits as components. The design presently lacks preemptive multitasking, ability to load firmware into the SRAMs used as logic elements, and input/output. Strategies are presented for adding these missing subsystems, again using only SRAM and trivial glue logic. A load-store architecture is employed with four clock cycles per instruction. Simulations indicate that a clock speed of at least 64 MHz is probable, corresponding to 16 million instructions per second (16 MIPS), despite the architecture containing no microprocessors, field programmable gate arrays, programmable logic devices, application specific integrated circuits, or other purchased complex logic. The lower speed, larger size, higher power consumption, and higher cost of an “SRAM minicomputer,” compared to traditional microcontrollers, may be offset by the fully open architecture—hardware and firmware—along with more rigorous user control, reliability, transparency, and auditability of the system. SRAM logic is also particularly well suited for building arithmetic logic units, and can implement complex operations such as population count, a hash function for associative arrays, or a pseudorandom number generator with good statistical properties in as few as eight clock cycles per 36-bit word processed. 36-bit unsigned multiplication can be implemented in software in 47 instructions or fewer (188 clock cycles). A general theory is developed for fast SRAM parallel multipliers should they be needed
Decomposition spaces in combinatorics
A decomposition space (also called unital 2-Segal space) is a simplicial object satisfying an exactness condition weaker than the Segal condition: just as the Segal condition expresses (up to homotopy) composition, the new condition expresses decomposition. It is a general framework for incidence (co)algebras. In the present contribution, after establishing a formula for the section coefficients, we survey a large supply of examples, emphasising the notion's firm roots in classical combinatorics. The first batch of examples, similar to binomial posets, serves to illustrate two key points: (1) the incidence algebra in question is realised directly from a decomposition space, without a reduction step, and reductions are often given by CULF functors; (2) at the objective level, the convolution algebra is a monoidal structure of species. Specifically, we encounter the usual Cauchy product of species, the shuffle product of L-species, the Dirichlet product of arithmetic species, the Joyal-Street external product of q-species and the Morrison `Cauchy' product of q-species, and in each case a power series representation results from taking cardinality. The external product of q-species exemplifies the fact that Waldhausen's S-construction on an abelian category is a decomposition space, yielding Hall algebras. The next class of examples includes Schmitt's chromatic Hopf algebra, the Fa\`a di Bruno bialgebra, the Butcher-Connes-Kreimer Hopf algebra of trees and several variations from operad theory. Similar structures on posets and directed graphs exemplify a general construction of decomposition spaces from directed restriction species. We finish by computing the M\Preprin
KAVUAKA: a low-power application-specific processor architecture for digital hearing aids
The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements
Hopf algebras and Markov chains: Two examples and a theory
The operation of squaring (coproduct followed by product) in a combinatorial
Hopf algebra is shown to induce a Markov chain in natural bases. Chains
constructed in this way include widely studied methods of card shuffling, a
natural "rock-breaking" process, and Markov chains on simplicial complexes.
Many of these chains can be explictly diagonalized using the primitive elements
of the algebra and the combinatorics of the free Lie algebra. For card
shuffling, this gives an explicit description of the eigenvectors. For
rock-breaking, an explicit description of the quasi-stationary distribution and
sharp rates to absorption follow.Comment: 51 pages, 17 figures. (Typographical errors corrected. Further fixes
will only appear on the version on Amy Pang's website, the arXiv version will
not be updated.
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