A Study of Nanometer Semiconductor Scaling Effects on Microelectronics Reliability

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. This dissertation provides a methodology on how to accomplish this and provides techniques for deriving the expected product-level reliability on commercial memory products. Competing mechanism theory and the multiple failure mechanism model are applied to two separate experiments; scaled SRAM and SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope Beta=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and key parameters

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

Energy-Efficient and Reliable Computing in Dark Silicon Era

Dark silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing in each technology generation. Moore’s law and Dennard scaling had been backed and coupled appropriately for five decades to bring commensurate exponential performance via single core and later muti-core design. However, recalculating Dennard scaling for recent small technology sizes shows that current ongoing multi-core growth is demanding exponential thermal design power to achieve linear performance increase. This process hits a power wall where raises the amount of dark or dim silicon on future multi/many-core chips more and more. Furthermore, from another perspective, by increasing the number of transistors on the area of a single chip and susceptibility to internal defects alongside aging phenomena, which also is exacerbated by high chip thermal density, monitoring and managing the chip reliability before and after its activation is becoming a necessity. The proposed approaches and experimental investigations in this thesis focus on two main tracks: 1) power awareness and 2) reliability awareness in dark silicon era, where later these two tracks will combine together. In the first track, the main goal is to increase the level of returns in terms of main important features in chip design, such as performance and throughput, while maximum power limit is honored. In fact, we show that by managing the power while having dark silicon, all the traditional benefits that could be achieved by proceeding in Moore’s law can be also achieved in the dark silicon era, however, with a lower amount. Via the track of reliability awareness in dark silicon era, we show that dark silicon can be considered as an opportunity to be exploited for different instances of benefits, namely life-time increase and online testing. We discuss how dark silicon can be exploited to guarantee the system lifetime to be above a certain target value and, furthermore, how dark silicon can be exploited to apply low cost non-intrusive online testing on the cores. After the demonstration of power and reliability awareness while having dark silicon, two approaches will be discussed as the case study where the power and reliability awareness are combined together. The first approach demonstrates how chip reliability can be used as a supplementary metric for power-reliability management. While the second approach provides a trade-off between workload performance and system reliability by simultaneously honoring the given power budget and target reliability

Prognostics and health management of power electronics

Prognostics and health management (PHM) is a major tool enabling systems to evaluate their reliability in real-time operation. Despite ground-breaking advances in most engineering and scientific disciplines during the past decades, reliability engineering has not seen significant breakthroughs or noticeable advances. Therefore, self-awareness of the embedded system is also often required in the sense that the system should be able to assess its own health state and failure records, and those of its main components, and take action appropriately. This thesis presents a radically new prognostics approach to reliable system design that will revolutionise complex power electronic systems with robust prognostics capability enhanced Insulated Gate Bipolar Transistors (IGBT) in applications where reliability is significantly challenging and critical. The IGBT is considered as one of the components that is mainly damaged in converters and experiences a number of failure mechanisms, such as bond wire lift off, die attached solder crack, loose gate control voltage, etc. The resulting effects mentioned are complex. For instance, solder crack growth results in increasing the IGBT’s thermal junction which becomes a source of heat turns to wire bond lift off. As a result, the indication of this failure can be seen often in increasing on-state resistance relating to the voltage drop between on-state collector-emitter. On the other hand, hot carrier injection is increased due to electrical stress. Additionally, IGBTs are components that mainly work under high stress, temperature and power consumptions due to the higher range of load that these devices need to switch. This accelerates the degradation mechanism in the power switches in discrete fashion till reaches failure state which fail after several hundred cycles. To this end, exploiting failure mechanism knowledge of IGBTs and identifying failure parameter indication are background information of developing failure model and prognostics algorithm to calculate remaining useful life (RUL) along with ±10% confidence bounds. A number of various prognostics models have been developed for forecasting time to failure of IGBTs and the performance of the presented estimation models has been evaluated based on two different evaluation metrics. The results show significant improvement in health monitoring capability for power switches.Furthermore, the reliability of the power switch was calculated and conducted to fully describe health state of the converter and reconfigure the control parameter using adaptive algorithm under degradation and load mission limitation. As a result, the life expectancy of devices has been increased. These all allow condition-monitoring facilities to minimise stress levels and predict future failure which greatly reduces the likelihood of power switch failures in the first place

Reliability Abstracts and Technical Reviews January - December 1970

Reliability Abstracts and Technical Reviews is an abstract and critical analysis service covering published and report literature on reliability. The service is designed to provide information on theory and practice of reliability as applied to aerospace and an objective appraisal of the quality, significance, and applicability of the literature abstracted

Thermal management and humidity based prognostics of high-power LED packages

While Light Emitting Diodes (LEDs) hold much potential as the future of lighting, the high junction temperatures generated during usage result in higher than expected degradation rates and premature failures ahead of the expected lifetime. This problem is especially under-addressed under conditions of high humidity, where there has been limited studies and standards to manage humidity based usage. This research provides an analysis of the factors that contribute to high junction temperatures and suggests prognostic techniques to aid in LED thermal management, specifically under humidity stress. First, this research investigates the effects of current, temperature and humidity on the electrical-optical-thermal (EOT) properties. Temperature rises within an LED because of input stressors which cause heat to build up: the input current, the operating and ambient temperature, and the relative humidity of the environment. Not only is there an accumulation of heat due to these factors that alter the thermal properties, but the electrical and optical characteristics are changed as well. By uncovering specific configurations causing the EOT performance to degrade under stress, better thermal management techniques can be employed. Second, this research proceeds to quantitatively link the EOT performance degradation to the humidity causal factor. The recent proliferation of LED usage in regions with high humidity has not corresponded with sufficient studies and standards governing LED test and usage under the humidity stressor. This has led to indeterminate use and consequentially, a lack of understanding of humidity based failures. A novel humidity based degradation model (HBDM) is successfully developed to gauge the impact of the humidity stressor by means of an index which is shown to be an effective predictor of colour degradation. This prognostication of the colour shift by the HBDM provides both academia and industry not only with an indicator of the physical degradation but also an assessment of the LED yellow-blue colour rendering stability, a critical application criterion. Using the HBDM parameters as indicators of the state of the LED, the degradation study is expanded in the development of a Distance Measure approach to isolate degraded samples exceeding a specified multivariate boundary. The HBDM and Distance Measure approach serve as powerful prognostic techniques in overall LED thermal management

Electric field-induced directed assembly of diblock copolymers and grain boundary grooving in metal interconnects

Das Anlegen eines elektrischen Feldes an Materialien hat eine faszinierende Wirkung. Unterschiedliche Werkstoffklassen sind einem externen elektrischen Feld entweder als ein Teil der Verarbeitung oder aufgrund der alleinigen Applikation ausgesetzt. Wenn das elektrische Feld für die Verarbeitung verwendet wird, kann dieses die Mikrostruktur in Metallen, Legierungen, Keramiken und Polymeren verändern, wodurch die physikalischen Eigenschaften verändert werden. Alternativ können mehrere Einsatzmöglichkeiten wie beispielsweise der Einsatz in elektronischen Geräten dazu führen, dass Materialien als Komponenten verwendet werden, die täglich intensiven Stromstärken ausgesetzt sind. Eine ständige Verlagerung der Atome kann zu Fehlern im offenen Stromkreis führen, wodurch die Zuverlässigkeit des gesamten Geräts beeinträchtigt wird. Mit Hilfe der Phasenfeldmethode wird in der vorliegenden Dissertation jeweils ein Anwendungsfall untersucht, in dem das elektrische Feld entweder positive oder negative Folgen haben kann. Im ersten Teil der Arbeit wird ein diffuses Grenzflächenmodell entwickelt und für die Untersuchung der gerichteten Selbstorganisation von symmetrischen Diblock-Copolymeren verwendet, die gleichzeitig durch das elektrische Feld, die Substrataffinität und die Beschränkung beeinflusst werden. Es werden verschiedene beschränkende Geometrien untersucht und eine Reihe an Phasendiagrammen für unterschiedliche Schichtdicken charakterisiert, die das Verhältnis zwischen dem elektrischen Feld und der Substratstärke zeigen. Zusätzlich zu der Ermittlung der vorhandenen parallelen, senkrechten und gemischten Lamellenphasen findet man, ähnlich wie bei den vorausgegangenen analytischen Berechnungen und experimentellen Beobachtungen, auch einen Bereich im Phasendiagramm, der einem Lamellenabstand der Größe eines halben Integrals entspricht, in dem hybride Morphologien wie Benetzungsschichten in der Nachbarschaft des Substrats koexistieren, die entweder Löcher in der Mitte der Schicht oder senkrechte zylinderförmige Bereiche aufweisen. Des Weiteren wird die Untersuchung auf drei Dimensionen erweitert, in denen die letztgenannte Morphologie als eine hexagonal perforierte (HPL) Lamellenphase charakterisiert wird. Erstmals wird gezeigt, dass durch ein elektrisches Feld ein Ordnungs-Ordnungs-übergang von einer Lamellenphase zu einer HPL-Phase hervorgerufen werden kann. Außerdem zeigt der kinetische Verlauf des Übergangs, dass es sich bei den perforierten Lamellen, die während des Übergangs von parallelen zu senkrechten Lamellen in Dünnschichten entstehen, um Zwischenstrukturen handelt. Im Folgenden werden verschiedene Beschädigungsarten erläutert, die aufgrund der Elektromigration (EM) in Nanoverbindungen durch die Rille der Korngrenze verursacht werden. Dazu wird ein einkomponentiges, polykristallines Phasenfeldmodell verwendet, das die Windstärke der Elektronen berücksichtigt. Das Modell und dessen numerische Umsetzung wird erst mit der scharfen Grenzflächentheorie von Mullins verglichen, bei der die thermische Rillenbildung durch Oberflächendiffusion vermittelt wird. Anschließend wird gezeigt, dass die Art der durch die fortschreitende Elektromigration verursachten Schädigung stark durch einen Fluss durch Grenzflächen beeinträchtigt werden kann, der aufgrund der Elektromigration stattfindet. Ein schneller atomarer Transport entlang der Oberfläche führt zu einer formerhaltenden Versetzung der Oberfläche, während der Schaden durch einen schnelleren atomaren Transport durch Grenzflächen in Form von interkristallinen Schlitzen mit einer formerhaltenden Spitze lokalisiert wird. Durch die Phasenfeldsimulationen wird die Funktion von krümmungs- und EM-induzierten heilenden Strömungen entlang der Oberfläche weiter hervorgehoben, die die Rille wieder auffüllen und die Schadensausbreitung verzögern. Erstmals wird ein numerisches Modell erweitert, um die räumlich-zeitliche Schadenseinleitung, die Ausbreitung, die Selbstheilung und die Kornvergröberung in dreidimensionalen Verbindungen zu untersuchen. Anschließend zeigt ein kritischer Vergleich der aus der scharfen Grenzflächenmethode und der Phasenfeldmethode gewonnenen Lösungen bezüglich der Rillenbildung, dass sowohl bei der Ermittlung der Rillenformen als auch beim Verlauf der Schadensart erhebliche Fehler entstehen können, wenn der durch die Elektromigration induzierte Oberflächenfluss in den Theorien der scharfen Grenzflächen nicht berücksichtigt wird. Zur Beseitigung der Diskrepanzen wird schließlich ein neues scharfes Grenzflächenmodell für finite Körner formuliert, das die zeitgleiche Kapillarwirkung und den durch die Elektromigration induzierten Oberflächen- und Grenzflächenfluss berücksichtigt. Die mit dem neuen Modell getroffenen Vorhersagen zeigen eine sehr gute Übereinstimmung mit dem Phasenfeldmodell. Durch die Ergebnisse der vorliegenden Arbeit wird die Durchführbarkeit und Anwendbarkeit der Phasenfeldmethode in Bezug auf die Erfassung der erforderlichen Physik des Problems und in Bezug auf die Bewältigung der mikrostrukturellen Entwicklung effizient und elegant in einem Phänomen verdeutlicht, das durch ein elektrisches Feld verursacht wird