11 research outputs found
ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ ๊ธฐ๋ฐ ๊ธฐ์ค ์ฃผํ์๋ฅผ ์ฌ์ฉํ์ง ์๋ ํด๋ก ๋ฐ ๋ฐ์ดํฐ ๋ณต์ ํ๋ก์ ์ค๊ณ ๋ฐฉ๋ฒ๋ก
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7ฮผs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.๋ณธ ๋
ผ๋ฌธ์ ๊ธฐ์ค ํด๋ญ์ด ์๋ ๊ณ ์, ์ ์ ๋ ฅ, ๊ด๋์ญ์ผ๋ก ๋์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก์ ์ค๊ณ๋ฅผ ์ ์ํ๋ค. ๊ธฐ์ค ํด๋ญ์ด ์๋ ๋์์ ์ํด์ ์๋ ์ฐ๋ ์์ ๊ฒ์ถ๊ธฐ์ ๊ธฐ๋ฐํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ฌ์ฉํ๋ ์ฃผํ์ ํ๋ ๋ฐฉ์์ด ์ฌ์ฉ๋๋ค. ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ์ ์ฃผํ์ ์ถ์ ์์์ ๋ถ์ํ๊ธฐ ์ํด ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์ ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ์๊ณ ์๋ฎฌ๋ ์ด์
์ ํตํด ๊ฒ์ฆํ์๋ค. ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์์ ํตํด ์ป์ ์ ๋ณด๋ฅผ ๋ฐํ์ผ๋ก ์๊ธฐ๊ณต๋ถ์ฐ์ ์ด์ฉํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์ง์ ๋น๋ก ๊ฒฝ๋ก์ ๋์งํธ ์ ๋ถ ๊ฒฝ๋ก๋ฅผ ํตํด ์ ์๋ ๊ธฐ์ค ํด๋ญ์ด ์๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ ๋ชจ๋ ์ธก์ ๊ฐ๋ฅํ ์กฐ๊ฑด์์ ์ฃผํ์ ์ ๊ธ์ ๋ฌ์ฑํ๋ ๋ฐ ์ฑ๊ณตํ์๊ณ , ๋ชจ๋ ๊ฒฝ์ฐ์์ ์ธก์ ๋ ์ฃผํ์ ์ถ์ ์๊ฐ์ 7ฮผs ์ด๋ด์ด๋ค. 40-nm CMOS ๊ณต์ ์ ์ด์ฉํ์ฌ ๋ง๋ค์ด์ง ์นฉ์ 0.032 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ 32 Gb/s์ ์๋์์ ๋นํธ์๋ฌ์จ 10-12 ์ดํ๋ก ๋์ํ์๊ณ , ์๋์ง ํจ์จ์ 32Gb/s์ ์๋์์ 1.0V ๊ณต๊ธ์ ์์ ์ฌ์ฉํ์ฌ 1.15 pJ/b์ ๋ฌ์ฑํ์๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 13
CHAPTER 2 BACKGROUNDS 14
2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14
2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24
2.2.1 OVERVIEW 24
2.2.2 JITTER 26
2.2.3 CDR JITTER CHARACTERISTICS 33
2.3 CDR ARCHITECTURES 39
2.3.1 PLL-BASED CDR โ WITH EXTERNAL REFERENCE CLOCK 39
2.3.2 DLL/PI-BASED CDR 44
2.3.3 PLL-BASED CDR โ WITHOUT EXTERNAL REFERENCE CLOCK 47
2.4 FREQUENCY ACQUISITION SCHEME 50
2.4.1 TYPICAL FREQUENCY DETECTORS 50
2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50
2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54
2.4.2 PRIOR WORKS 56
CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58
3.1 OVERVIEW 58
3.2 PROPOSED FREQUENCY DETECTOR 62
3.2.1 MOTIVATION 62
3.2.2 PATTERN HISTOGRAM ANALYSIS 68
3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75
3.3 CIRCUIT IMPLEMENTATION 83
3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83
3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85
3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87
3.4 MEASUREMENT RESULTS 89
CHAPTER 4 CONCLUSION 99
APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100
BIBLIOGRAPHY 108
์ด ๋ก 122๋ฐ
Modeling and Design of Architectures for High-Speed ADC-Based Serial Links
There is an ongoing dramatic rise in the volume of internet traffic. Standards such as
56Gb/s OIF very short reach (VSR), medium reach (MR) and long reach (LR) standards for chip
to chip communication over channels with up to 10dB, 20dB and 30dB insertion loss at the PAM
4 Nyquist frequency, respectively, are being adopted. These standards call for the spectrally
efficient PAM-4 signaling over NRZ signaling. PAM-4 signaling offers challenges such as a
reduced SNR at the receiver, susceptibility to nonlinearities and increased sensitivity to residual
ISI. Equalization provided by traditional mixed signal architectures can be insufficient to achieve
the target BER requirements for very long reach channels. ADC-based receiver architectures for
PAM-4 links take advantage of the more powerful equalization techniques, which lend themselves
to easier and robust digital implementations, to extend the amount of insertion loss that the receiver
can handle. However, ADC-based receivers can consume more power compared to mixed-signal
implementations. Techniques that model the receiver performance to understand the various
system trade-offs are necessary.
This research presents a fast and accurate hybrid modeling framework to efficiently
investigate system trade-offs for an ADC-based receiver. The key contribution being the addition
of ADC related non-idealities such as quantization noise in the presence of integral and differential
nonlinearities, and time-interleaving mismatch errors such as gain mismatch, bandwidth
mismatch, offset mismatch and sampling skew.
The research also presents a 52Gb/s ADC-based PAM-4 receiver prototype employing
a 32-way time-interleaved, 2-bit/stage, 6-bit SAR ADC and a DSP with a 12-tap FFE and a 2-tap
DFE. A new DFE architecture that reduces the complexity of a PAM-4 DFE to that of an NRZ
DFE while simultaneously nearly doubling the maximum achievable data rate is presented. The
receiver architecture also includes an analog front-end (AFE) consisting of a programmable two
stage CTLE. A digital baud-rate CDRโs utilizing a Mueller-Muller phase detector sets the sampling
phase. Measurement results show that for 32Gb/s operation a BER < 10โปโน is achieved for a 30dB
loss channel while for 52 Gb/s operation achieves a BER < 10โปโถ for a 31dB loss channel with a
power efficiency of 8.06pj/bit
Recommended from our members
Built-in self test of RF subsystems
textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin
Design of CMOS integrated phase-locked loops for multi-gigabits serial data links
High-speed serial data links are quickly gaining in popularity and replacing the
conventional parallel data links in recent years when the data rate of communication
exceeds one gigabits per second. Compared with parallel data links, serial data links are
able to achieve higher data rate and longer transfer distance. This dissertation is focused on
the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks
used in multi-gigabits serial data link transceivers.
Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are
modeled and analyzed. The steady-state behavior of BPLLs is derived with combined
discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs
are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC-
192, the mainstream standard for optical serial data links, is presented. The CDR is based
on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked
loop based on a quad-level phase detector and a linear frequency-locked loop based on a
linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in
0.18 รรยผm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter
generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance
exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential
divide-by-eight injection-locked frequency divider with low power dissipation is presented.
The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It
has a maximum operating frequency of 18 GHz. The ratio of locking range over center
frequency is up to 50%. The prototype chip is implemented in 0.18 รรยผm CMOS technology
and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques
of fully differential charge pumps are discussed. Techniques are proposed to minimize the
nonidealities associated with a fully differential charge pump, including differential
mismatch, output current variation, low-speed glitches and high-speed glitches. The
performance improvement brought by the techniques is verified with simulations of
schematics designed in 0.35 รรยผm CMOS technology
Analysis and design of an 80 Gbit/sec clock and data recovery prototype
La demande croissante de toujours plus de dรฉbit pour les tรฉlรฉcommunications entraine une augmentation de la frรฉquence de fonctionnement des liaisons sรฉries. Cette demande se retrouve aussi dans les systรจmes embarquรฉs du fait de l'augmentation des performances des composants et pรฉriphรฉriques. Afin de s'assurer que le train de donnรฉes est bien rรฉceptionnรฉ, un circuit de restitution d'horloge et de donnรฉes est placรฉ avant tout traitement du cotรฉ du rรฉcepteur. Dans ce contexte, les activitรฉs de recherche prรฉsentรฉes dans cette thรจse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous dรฉtaillerons le comparateur de phase qui joue un rรดle critique dans un tel systรจme. Cette thรจse prรฉsente un comparateur de phase ayant comme avantage d'avoir une mode de fenรชtrage et une frรฉquence de fonctionnement rรฉduite. La topologie spรฉciale utilisรฉe pour la CDR est dรฉcrite, et la thรฉorie relative aux oscillateurs verrouillรฉs en injection est expliquรฉe. L'essentiel du travail de recherche s'est concentrรฉe sur la conception et le layout d'une restitution d'horloge dans le domaine millimรฉtrique, ร 80 Gbps. Pour cela plusieurs prototypes ont รฉtรฉ rรฉalisรฉs en technologie BiCMOS 130 nm de STMicrolectronics.The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF
Evaluating Techniques for Wireless Interconnected 3D Processor Arrays
In this thesis the viability of a wireless interconnect network for a highly parallel computer is investigated. The main theme of this thesis is to project the performance of a wireless network used to connect the processors in a parallel machine of such design. This thesis is going to investigate new design opportunities a wireless interconnect network can offer for parallel computing.
A simulation environment is designed and implemented to carry out the tests. The results have shown that if the available radio spectrum is shared effectively between building blocks of the parallel machine, there are substantial chances to achieve high processor utilisation. The results show that some factors play a major role in the performance of such a machine. The size of the machine, the size of the problem and the communication and computation capabilities of each element of the machine are among those factors. The results show these factors set a limit on the number of nodes engaged in some classes of tasks. They have shown promising potential for further expansion and evolution of our idea to new architectural opportunities, which is discussed by the end of this thesis.
To build a real machine of this type the architects would need to solve a number of challenging problems including heat dissipation, delivering electric power and Chip/board design; however, these issues are not part of this thesis and will be tackled in future
Design of High-Speed CMOS Interface Circuits for Optical Communications
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ)-- ์์ธ๋ํ๊ต ๋ํ์ ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2017. 8. ์ ๋๊ท .The bandwidth requirement of wireline communications has increased ex-ponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effect, dielectric loss, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul net-works and metropolitan area networks, to the medium- and short-reach com-munication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challeng-es are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics that has long been investigated by a number of research groups. De-spite inherent incompatibility of silicon with the photonic world, silicon pho-tonics is promising and is the only solution that can leverage the mature CMOS technologies.
In this thesis, we summarize the current status of silicon photonics and pro-vide the prospect of the optical interconnection. We also present key circuit techniques essential to the implementation of high-speed and low-power optical receivers. And then, we propose optical receiver architectures satisfying the aforementioned requirements with novel circuit techniques.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 6
CHAPTER 2 BACKGROUND OF OPTICAL COMMUNICATION 7
2.1 OVERVIEW OF OPTICAL LINK 7
2.2 SILICON PHOTONICS 11
2.3 HYBRID INTEGRATION 22
2.4 SILICON-BASED PHOTODIODES 28
2.4.1 BASIC TERMINOLOGY 28
2.4.2 SILICON PD 29
2.4.3 GERMANIUM PD 32
2.4.4 INTEGRATION WITH WAVEGUIDE 33
CHAPTER 3 CIRCUIT TECHNIQUES FOR OPTICAL RECEIVER 35
3.1 BASIS OF TRANSIMPEDANCE AMPLIFIER 35
3.2 TOPOLOGY OF TIA 39
3.2.1 RESISTOR-BASED TIA 39
3.2.2 COMMON-GATE-BASED TIA 41
3.2.3 FEEDBACK-BASED TIA 44
3.2.4 INVERTER-BASED TIA 47
3.2.5 INTEGRATING RECEIVER 48
3.3 BANDWIDTH EXTENSION TECHNIQUES 49
3.3.1 INDUCTOR-BASED TECHNIQUE 49
3.3.2 EQUALIZATION 61
3.4 CLOCK AND DATA RECOVERY CIRCUITS 66
3.4.1 CDR BASIC 66
3.4.2 CDR EXAMPLES 68
CHAPTER 4 LOW-POWER OPTICAL RECEIVER FRONT-END 73
4.1 OVERVIEW 73
4.2 INVERTER-BASED TIA WITH RESISTIVE FEEDBACK 74
4.3 INVERTER-BASED TIA WITH RESISTIVE AND INDUCTIVE FEEDBACK 81
4.4 CIRCUIT IMPLEMENTATION 89
4.5 MEASUREMENT RESULTS 93
CHAPTER 5 BANDWIDTH- AND POWER-SCALABLE OPTICAL RECEIVER FRONT-END 96
5.1 OVERVIEW 96
5.2 BANDWIDTH AND POWER SCALABILITY 97
5.3 GM STABILIZATION 98
5.4 OVERALL BLOCK DIAGRAM OF RECEIVER 104
5.5 MEASUREMENT RESULTS 111
CHAPTER 6 CONCLUSION 118
BIBLIOGRAPHY 120
์ด ๋ก 131Docto
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