A VLSI implementation of the collision avoidance switch protocol for CAMB tree LANs

To solve a performance bottle neck in random access LANs due to packet collisions and their resolution, collision avoidance switches are introduced. These switches allow random access protocols to achieve high performance by resolving collisions among packets. A conventional hardware implementation of these switches is the use of TTL chips. In this implementation; a handful of TTL chips are required to forma single switch (e.g., 18 TTL chips are needed for an implementation of the CAMB switch [7]). Thus, implementation of a complete network, which requires several of these switches, could very well result in a large and complex hardware system.Today's modern chip technology allows us to pack large quantity of logic in a single chip. By transferring the conventional implementation of the collision avoidance switches into a VLSI chip, the complexity of the resultant hardware is greatly reduced, not to mention the improvement in hardware performance and ease of packaging.This report provides an overall study of the collision avoidance protocols for the tree LANs with emphasis on the implementation of collision avoidance switches. Hardware implementations of sorne of these switches are discussed. And a VLSI implementation of the CAMB switch protocol is introduced

Modelling of Heavy Vehicle Transmission Synchronizer using Constrained Lagrangian Formalism

Robust and efficient synchronizers are keys elements to ensure good gear shift in heavy vehicles. In order to improve existing as well as develop new synchronizers, efficient simulation tools are needed. In this contribution, a mechanical system with 5 degrees of freedom modelling a generic synchronizer consisting of engaging sleeve, synchronizer ring and gearwheel are considered. Due to the design of the different components and their interactions the synchronizing process is described in terms of different steps or phases; presynchronization, main synchronization, blocker transition and engagement. The four main phases are further divided into sub-phases. To study the whole process in a unified manner, Constrained Lagrangian Formalism (CLF) turns out to be a suitable method in which the interactions between components (sleeve, synchronizer ring and gearwheel) are described by unilateral or/and bilateral constraints imposed on generalized coordinates of the system during different phases. Using CLF a mathematical model of a generic synchronizer is developed and represented by the system of differential-algebraic equations. Kinematics and kinetics of the generic synchronizer are modelled for each sub-phase. The sleeve is considered as a master and the gearwheel is considered as a slave. The statement of the dynamics problem for a generic synchronizer is given and the numerical algorithm is implemented in Matlab for solving the differential-algebraic equations resulting from CLF. The generic synchronizer computational model is adapted to available experimental setup and validated using obtained measurement data. Sensitivity of the synchronization time is studied varying the cone angle, coefficient of dry friction and sleeve force. Effect of driveline vibrations on synchronization performance is also studied

module-lab-2.3-Basic Building Blocks for Synchronization

Practice & La

On a Hybrid Preamble/Soft-Output Demapper Approach for Time Synchronization for IEEE 802.15.6 Narrowband WBAN

In this paper, we present a maximum likelihood (ML) based time synchronization algorithm for Wireless Body Area Networks (WBAN). The proposed technique takes advantage of soft information retrieved from the soft demapper for the time delay estimation. This algorithm has a low complexity and is adapted to the frame structure specified by the IEEE 802.15.6 standard for the narrowband systems. Simulation results have shown good performance which approach the theoretical mean square error limit bound represented by the Cramer Rao Bound (CRB)

New Concept of PLC Modems: Multi-Carrier System for Frequency Selective Slow-Fading Channels Based on Layered SCCC Turbocodes

The article introduces a novel concept of a PLC modem as a complement to the existing G3 and PRIME standards for communications using medium- or high-voltage overhead or cable lines. The proposed concept is based on the fact that the levels of impulse noise and frequency selectivity are lower on high-voltage lines than on low-voltage ones. Also, the demands for “cost-effective” circuitry design are not so crucial as in the case of modems for low-voltage level. In contract to these positive conditions, however, there is the need to overcome much longer distances and to take into account low SNR on the receiving side. With respect to the listed reasons, our concept makes use of MCM, instead of OFDM. The assumption of low SNR is compensated through the use of an efficient channel coding based on a serially concatenated turbo code. In addition, MCM offers lower latency and PAPR compared to OFDM. Therefore, when using MCM, it is possible to excite the line with higher power. The proposed concept has been verified during experimental transmission of testing data over a real, 5 km long, 22kV overhead line

Using MCD-DVS for dynamic thermal management performance improvement

With chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for power reduction in the past and some on thermal management more recently have contributed to alleviate this problem. Probably the most important thermal control technique is dynamic voltage and frequency scaling (DVS) which allows for almost cubic reduction in power with worst-case performance penalty only linear. So far, DVS techniques for temperature control have been studied at the chip level. Finer grain DVS is feasible if a globally-asynchronous locally-synchronous (GALS) design style is employed. GALS, also known as multiple-clock domain (MCD), allows for an independent voltage and frequency control for each one of the clock domains that are part of the chip. There are several studies on DVS for GALS that aim to improve energy and power efficiency but not temperature. This paper proposes and analyses the usage of DVS at the domain level to control temperature in a clustered MCD microarchitecture with the goal of improving the performance of applications that do not meet the thermal constraints imposed by the designers.Peer ReviewedPostprint (published version

Quality-Driven Disorder Handling for M-way Sliding Window Stream Joins

Sliding window join is one of the most important operators for stream applications. To produce high quality join results, a stream processing system must deal with the ubiquitous disorder within input streams which is caused by network delay, asynchronous source clocks, etc. Disorder handling involves an inevitable tradeoff between the latency and the quality of produced join results. To meet different requirements of stream applications, it is desirable to provide a user-configurable result-latency vs. result-quality tradeoff. Existing disorder handling approaches either do not provide such configurability, or support only user-specified latency constraints. In this work, we advocate the idea of quality-driven disorder handling, and propose a buffer-based disorder handling approach for sliding window joins, which minimizes sizes of input-sorting buffers, thus the result latency, while respecting user-specified result-quality requirements. The core of our approach is an analytical model which directly captures the relationship between sizes of input buffers and the produced result quality. Our approach is generic. It supports m-way sliding window joins with arbitrary join conditions. Experiments on real-world and synthetic datasets show that, compared to the state of the art, our approach can reduce the result latency incurred by disorder handling by up to 95% while providing the same level of result quality.Comment: 12 pages, 11 figures, IEEE ICDE 201