A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications

Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer. Volume 1: FTMP principles of operation

The basic organization of the fault tolerant multiprocessor, (FTMP) is that of a general purpose homogeneous multiprocessor. Three processors operate on a shared system (memory and I/O) bus. Replication and tight synchronization of all elements and hardware voting is employed to detect and correct any single fault. Reconfiguration is then employed to repair a fault. Multiple faults may be tolerated as a sequence of single faults with repair between fault occurrences

Design study of error-detecting and error correcting shift register

Design of error detecting and error correcting shift registe

New and improved demonstrations, each illustrating a single scientific paper

Thesis (Ed.M.)--Boston Universit

A low-noise small signal sensing scheme in voltage mode for high density magnetoresistive memories

Magnetoresistive memory (MRAM) technology which successfully combines integrated circuit and magnetic thin film processes to achieve non-volatile, radiation hard, random access read/write memories, has shown rapid development in the past few years. A considerable amount of research effort is directed towards improving the bit density, which involves the design of denser cells with improved signal levels, and development of suitable sensing schemes. This dissertation presents work done in developing the low noise front end of a multistage small signal sensing scheme, designed for high density MRAMs. The design scheme uses a new sensing mode called \u27voltage mode\u27, instead of \u27current mode\u27 which is presently in use. An analysis of both current mode and voltage mode sensing has been carried out to show that voltage mode has superior performance. This scheme uses self referencing to reduce the memory cell area. All critical deterrant factors that affect this technique have been analyzed and suitable strategies have been developed to minimize their effect. This scheme senses a nominal signal of 0.4 mV in the presence of large voltage offsets which are 100 mV in the worst case. The memory cell area has been reduced to 25 square microns per bit and the read access time is 800 ns

Simulations of ultra-low power non-volatile cells for random access memory

Dynamic random-access memory (DRAM), which represents 99% of random access memory (RAM), is fast and has excellent endurance, but suffers from disadvantages such as short data retention time (volatility) and loss of data during readout (destructive read). As a consequence, it requires persistent data refreshing, increasing energy consumption, degrading performance and limiting scaling capacity. It is therefore desirable that the next generation of RAM will be non-volatile (NVRAM), low power, high endurance, fast and non-destructively read. Here, we report on a new form of NVRAM: a compound-semiconductor charge-storage memory that exploits quantum phenomena for its operational advantages. Simulations show that the device is extremely low power, with 100 times lower switching energy per unit area than DRAM, but with similar operating speeds. Non-volatility is achieved due to the extraordinary band offsets of InAs and AlSb, providing a large energy barrier (2.1 eV) which prevents the escape of electrons. Based on the simulation results, an NVRAM architecture is proposed for which extremely low disturb-rates are predicted as a result of the quantum-mechanical resonant-tunnelling mechanism used to write and erase

A study on virtual reality and developing the experience in a gaming simulation

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Masters by ResearchVirtual Reality (VR) is an experience where a person is provided with the freedom of viewing and moving in a virtual world [1]. The experience is not constrained to a limited control. Here, it was triggered interactively according to the user’s physical movement [1] [2]. So the user feels as if they are seeing the real world; also, 3D technologies allow the viewer to experience the volume of the object and its prospection in the virtual world [1]. The human brain generates the depth when each eye receives the images in its point of view. For learning for and developing the project using the university’s facilities, some of the core parts of the research have been accomplished, such as designing the VR motion controller and VR HMD (Head Mount Display), using an open source microcontroller. The VR HMD with the VR controller gives an immersive feel and a complete VR system [2]. The motive was to demonstrate a working model to create a VR experience on a mobile platform. Particularly, the VR system uses a micro electro-mechanical system to track motion without a tracking camera. The VR experience has also been developed in a gaming simulation. To produce this, Maya, Unity, Motion Analysis System, MotionBuilder, Arduino and programming have been used. The lessons and codes taken or improvised from [33] [44] [25] and [45] have been studied and implemented

Research on a non-destructive fluidic storage control device

Fluidic memory device with associated fluidic alpha numerical displa

Engineering study for a mass memory system for advanced spacecrafts Final report, 1 Dec. 1969 - 1 Jul. 1970

Mass memory system for advanced spacecraf

Development of a fiber optic high temperature strain sensor

From 1 Apr. 1991 to 31 Aug. 1992, the Georgia Tech Research Institute conducted a research program to develop a high temperature fiber optic strain sensor as part of a measurement program for the space shuttle booster rocket motor. The major objectives of this program were divided into four tasks. Under Task 1, the literature on high-temperature fiber optic strain sensors was reviewed. Task 2 addressed the design and fabrication of the strain sensor. Tests and calibration were conducted under Task 3, and Task 4 was to generate recommendations for a follow-on study of a distributed strain sensor. Task 4 was submitted to NASA as a separate proposal