Training Passive Photonic Reservoirs with Integrated Optical Readout

As Moore's law comes to an end, neuromorphic approaches to computing are on the rise. One of these, passive photonic reservoir computing, is a strong candidate for computing at high bitrates (> 10 Gbps) and with low energy consumption. Currently though, both benefits are limited by the necessity to perform training and readout operations in the electrical domain. Thus, efforts are currently underway in the photonic community to design an integrated optical readout, which allows to perform all operations in the optical domain. In addition to the technological challenge of designing such a readout, new algorithms have to be designed in order to train it. Foremost, suitable algorithms need to be able to deal with the fact that the actual on-chip reservoir states are not directly observable. In this work, we investigate several options for such a training algorithm and propose a solution in which the complex states of the reservoir can be observed by appropriately setting the readout weights, while iterating over a predefined input sequence. We perform numerical simulations in order to compare our method with an ideal baseline requiring full observability as well as with an established black-box optimization approach (CMA-ES).Comment: Accepted for publication in IEEE Transactions on Neural Networks and Learning Systems (TNNLS-2017-P-8539.R1), copyright 2018 IEEE. This research was funded by the EU Horizon 2020 PHRESCO Grant (Grant No. 688579) and the BELSPO IAP P7-35 program Photonics@be. 11 pages, 9 figure

The future of computing beyond Moore's Law.

Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'

CMOS compatible athermal silicon microring resonators

Silicon photonics promises to alleviate the bandwidth bottleneck of modern day computing systems. But silicon photonic devices have the fundamental problem of being highly sensitive to ambient temperature fluctuations due to the high thermo-optic (TO) coefficient of silicon. Most of the approaches proposed to date to overcome this problem either require significant power consumption or incorporate materials which are not CMOS-compatible. Here we demonstrate a new class of optical devices which are passively temperature compensated, based on tailoring the optical mode confinement in silicon waveguides. We demonstrate the operation of a silicon photonic resonator over very wide temperature range of greater than 80 degrees. The fundamental principle behind this work can be extended to other photonic structures such as modulators, routers, switches and filters.Comment: 9 pages, 4 figure

Silicon optical modulators

Optical technology is poised to revolutionise short reach interconnects. The leading candidate technology is silicon photonics, and the workhorse of such interconnect is the optical modulator. Modulators have been improved dramatically in recent years. Most notably the bandwidth has increased from the MHz to the multi GHz regime in little more than half a decade. However, the demands of optical interconnect are significant, and many questions remain unanswered as to whether silicon can meet the required performance metrics. Minimising metrics such as the energy per bit, and device footprint, whilst maximising bandwidth and modulation depth are non trivial demands. All of this must be achieved with acceptable thermal tolerance and optical spectral width, using CMOS compatible fabrication processes. Here we discuss the techniques that have, and will, be used to implement silicon optical modulators, as well as the outlook for these devices, and the candidate solutions of the future

lOptical coupling structure made by imprinting between single-mode polymer waveguide and embedded VCSEL

Polymer-based integrated optics is attractive for inter-chip optical interconnection applications, for instance, for coupling photonic devices to fibers in high density packaging. In such a hybrid integration scheme, a key challenge is to achieve efficient optical coupling between the photonic chips and waveguides. With the single-mode polymer waveguides, the alignment tolerances become especially critical as compared to the typical accuracies of the patterning processes. We study novel techniques for such coupling requirements. In this paper, we present a waveguide-embedded micro-mirror structure, which can be aligned with high precision, even active alignment method is possible. The structure enables 90 degree bend coupling between a single-mode waveguide and a vertical-emitting/detecting chip, such as, a VCSEL or photodiode, which is embedded under the waveguide layer. Both the mirror structure and low-loss polymer waveguides are fabricated in a process based mainly on the direct-pattern UV nanoimprinting technology and on the use of UV-curable polymeric materials. Fabrication results of the coupling structure with waveguides are presented, and the critical alignment tolerances and manufacturability issues are discussed