Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

2 GHz +14 dBm CMOS power amplifier for Low Power Wide Area Networks

Abstract. The design of a radiofrequency power amplifier (RF PA) for narrowband low-power wide area networks is presented in this thesis. Particularly, this RF PA is compliant with the 3GPP TS 36.101 standard for a NB1 device within the Power Class 6. To minimize silicon area consumption, this CMOS RF PA employs a single-ended single-stage topology, avoiding inter-stage matching network inductors and output baluns. This RF PA produces +14 dBm of output power with a PAE of 25% and an EVM better than 4% (−28 dB). Also, its out-of-band and spurious emissions satisfy the standard specifications with a large margin. Furthermore, it provides high ruggedness, tolerating an antenna mismatch with a VSWR of 8:1

RF-CMOS Switched-Capacitor Power Amplifier for NB-IoT RF transceivers

The increasing market of Narrowband Internet of Things (NB-IoT) applications brings new challenges and constrains in the design of fully integrated transmission architectures, capable of delivering the desired output power with the highest efficiency and linearity, ensuring the longest battery lifetime of the devices. This work is focused on the study and implementation of the most power consuming block within the transmission chain: the Power Amplifier (PA). In this regard, a Switched Capacitor Power Amplifier (SCPA) is designed to operate at a frequency of 0.9 GHz and aiming the maximum output power allowed by the standard of 23 dBm. The final architecture includes a matching network that connects to eight unit PA cells through an LC filter. Each unit PA cell is made of a cascoded class-D PA, two drivers, a level shifter and two selection logic blocks. All the blocks were developed using RF components from a UMC 130nm CMOS process with a 1.2V/2.4V supply voltage. The results show that the architecture is able to produce a maximum output power of 15.61 dBm with a maximum Power Added Efficiency (PAE) of 26.52% and a Total Harmonic Distortion (THD) of 0.68%. In the same conditions, the measured HD2 and HD3 are of -70.23dBc and -43.41dBc, respectively. Additionally, a modulation stage was implemented in VerilogA in order to evaluate the impact of sending different symbols in the SCPA performance. The block, designed for a 16 QAM modulation, is responsible for generating both the number of unit PA cells to be selected and the phase of the clock connected to each PA cell, depending on the amplitude and phase of the constellation points being transmitted.O mercado crescente de aplicações IoT de largura de banda estreita coloca novos desafios e restrições no desenvolvimento de arquiteturas de transmissão totalmente integradas, capazes de produzir a potência desejada com o máximo de eficiência e linearidade possí- veis, de forma a garantir o maior tempo de vida de bateria dos dispositivos. Este trabalho foca-se no estudo e implementação do bloco da cadeia de transmissão que mais consome: o amplificador de potência. Neste sentido, um amplificador de potência de condensadores comutados é desenhado para operar à frequência de 0.9GHz com o objetivo de produzir à sua saída o valor de potência máxima permitida pelo standard de 23dBm. A arquitetura inclui uma malha de adaptação que liga a oito PAs unitários através de um filtro LC. Cada PA unitário consiste num amplificador de potencia class-D cascoded, dois drivers, um level shifter e dois blocos de lógica de seleção. Todos estes blocos foram desenvolvidos usando componentes RF da tecnologia CMOS 130nm da UMC com uma tensão de alimentação de 1.2V/2.4V. Os resultados mostram que a arquitetura é capaz de produzir uma potência à saída de 15.61dBm, com uma PAE de 26.52% e uma distorção harmónica total de 0.68%. Nas mesmas condições, os valores medidos da HD2 e HD3 são de -70.23dBc e -43.41dBc, respetivamente. Adicionalmente, um andar de modulação foi implementado em VerilogA, de forma a avaliar o impacto de enviar diferentes símbolos na performance do amplificador. Este bloco, desenvolvido para uma modulacao 16QAM, é responsável por gerar o número de unidades de PA a serem selecionados e o relógio de fase que liga a cada PA unitário, dependendo da amplitude e fase dos pontos da constelação a serem transmitidos

High speed IC designs for low power short reach optical links

In this thesis, I have briefly introduced the background of my PhD research, current state-of-the-art design, and my PhD research objectives. Then, I demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM’s Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC’s ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM- 4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm 2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only. In the future, system level analysis should be carried out to investigate the critical pattern issue of the PAM4 optical transmitter. The potential solutions toward 1pJ/bit are given (lumped EAM and micro-ring modulator). In addition, the advanced modulation formats (16 QAM, discrete multitone modulation, and FFE) are presented based on the switched capacitor approach