A Programmable Window Comparator for Analog Online Testing

This paper discusses the challenge of designing window comparators for analog online testing applications. A programmable window comparator with adaptive error threshold is presented. Experimental results demonstrate that improved fault detection capability is achieved by using the proposed design. Measurement results of the fabricated comparator circuit are also presented

A Fully Programmable Analog Window Comparator

This paper presents a novel design of analog window comparator circuit. The comparator can adaptively adjust its error threshold according to the magnitude of input signal levels. In addition, the circuit can be digitally programmed to realize different error threshold adapting schemes. The design is fabricated using a 0.18mum CMOS technology. Testing results of the fabricated chip are also presented

A Methodology to Perform Online Self-Testing for Field-Programmable Analog Array Circuits

This paper presents a methodology to perform online self-testing for analog circuits implemented on field-programmable analog arrays (FPAAs). It proposes to partition the FPAA circuit under test into subcircuits. Each subcircuit is tested by replicating the subcircuit with programmable resources on the FPAA chip, and comparing the outputs of the subcircuit and its replication. To effectively implement the proposed methodology, this paper proposes a simple circuit partition method and develops techniques to address circuit stability problems that are often encountered in the proposed testing method. Furthermore, error sources in the proposed testing circuit are studied and methods to improve the accuracy of testing results are presented. Finally, experimental results are presented to demonstrate the validity of the proposed methodology

Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques

This paper presents techniques to model the impact of parametric faults on the performance of programmable capacitor arrays (PCAs). Closed-form equations are derived for estimating ranges of parametric faults that can be detected by integrator-based PCA testing circuits. Methods to improve PCA testing efficiency are discussed and experimental results are reported

Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications

This paper presents a novel window comparator circuit whose error threshold can be adaptively adjusted according to its input signal levels. It is ideal for analog online testing applications. Advantages of adaptive comparator error thresholds over constant or relative error thresholds in analog testing applications are discussed. Analytical equations for guiding the design of proposed comparator circuitry are derived. The proposed comparator circuit has been designed and fabricated using a CMOS 0.18mu technology. Measurement results of the fabricated chip are presented

A major electronics upgrade for the H.E.S.S. Cherenkov telescopes 1-4

The High Energy Stereoscopic System (H.E.S.S.) is an array of imaging atmospheric Cherenkov telescopes (IACTs) located in the Khomas Highland in Namibia. It consists of four 12-m telescopes (CT1-4), which started operations in 2003, and a 28-m diameter one (CT5), which was brought online in 2012. It is the only IACT system featuring telescopes of different sizes, which provides sensitivity for gamma rays across a very wide energy range, from ~30 GeV up to ~100 TeV. Since the camera electronics of CT1-4 are much older than the one of CT5, an upgrade is being carried out; first deployment was in 2015, full operation is planned for 2016. The goals of this upgrade are threefold: reducing the dead time of the cameras, improving the overall performance of the array and reducing the system failure rate related to aging. Upon completion, the upgrade will assure the continuous operation of H.E.S.S. at its full sensitivity until and possibly beyond the advent of CTA. In the design of the new components, several CTA concepts and technologies were used and are thus being evaluated in the field: The upgraded read-out electronics is based on the NECTAR readout chips; the new camera front- and back-end control subsystems are based on an FPGA and an embedded ARM computer; the communication between subsystems is based on standard Ethernet technologies. These hardware solutions offer good performance, robustness and flexibility. The design of the new cameras is reported here.Comment: Proceedings of the 34th International Cosmic Ray Conference, 30 July- 6 August, 2015, The Hague, The Netherland

An Analog Checker with Programmable Adaptive Error Threshold

This paper presents an analog checker whose error threshold can be adaptively adjusted according to its input signal levels. In addition, the proposed circuit can be programmed to implement different adaptive schemes. Factors that affect the stability and accuracy of the proposed design are investigated. Finally, simulation results are presented

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing

The camera of the fifth H.E.S.S. telescope. Part I: System description

In July 2012, as the four ground-based gamma-ray telescopes of the H.E.S.S. (High Energy Stereoscopic System) array reached their tenth year of operation in Khomas Highlands, Namibia, a fifth telescope took its first data as part of the system. This new Cherenkov detector, comprising a 614.5 m^2 reflector with a highly pixelized camera in its focal plane, improves the sensitivity of the current array by a factor two and extends its energy domain down to a few tens of GeV. The present part I of the paper gives a detailed description of the fifth H.E.S.S. telescope's camera, presenting the details of both the hardware and the software, emphasizing the main improvements as compared to previous H.E.S.S. camera technology.Comment: 16 pages, 13 figures, accepted for publication in NIM