System and circuitry to provide stable transconductance for biasing

An amplifier system can include an input amplifier configured to receive an analog input signal and provide an amplified signal corresponding to the analog input signal. A tracking loop is configured to employ delta modulation for tracking the amplified signal, the tracking loop providing a corresponding output signal. A biasing circuit is configured to adjust a bias current to maintain stable transconductance over temperature variations, the biasing circuit providing at least one bias signal for biasing at least one of the input amplifier and the tracking loop, whereby the circuitry receiving the at least one bias signal exhibits stable performance over the temperature variations. In another embodiment the biasing circuit can be utilized in other applications

Wireless sensor platform for harsh environments

Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna

A programmable microsystem using system-on-chip for real-time biotelemetry

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm × 5 mm silicon chip using a 0.6 μm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm × 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10<sup>-</sup><sup>3</sup> using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power

Wireless neural recording with single low-power integrated circuit

Journal ArticleWe present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- m 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor

Estudio y diseño de dos placas de intercambio de datos de inclinación y posición entre dos cubesats

El grupo de investigación DISEN con sede en el Campus de Terrassa de la UPC está intentando impulsar el proyecto de la implementación de una infraestructura de comunicaciones basada en el enlace óptico de CubeSats. Mediante este tipo de comunicación, se podría obtener un mayor data-rate y un menor consumo de potencia que en los actuales sistemas de radiofrecuencia. Para poder realizar este enlace óptico, es necesario que el rayo láser proveniente de uno de los satélites se centre de forma muy precisa en el foto-detector del otro satélite. Para realizar dicho centrado, ambos satélites deberán conocer a priori la posición e inclinación de ambos, información que deberán intercambiarse mediante radiofrecuencia. El presente TFG versa sobre el diseño del subsistema de intercambio de datos de posición e inclinación entre dos CubeSats. Concretamente, el diseño de dos placas PCB formadas por un módulo GPS, para obtener la posición de los CubeSats; un módulo IMU, para obtener sus actitudes; un módulo de radio UHF, para enviar datos entre los dos CubeSats por radiofrecuencia; y un módulo Bluetooth para poder enlazar el sistema con el ordenador de base. Además, las placas cuentan con un microcontrolador para procesar y almacenar la información de dichos módulos

TPMS Receiver Hacking

In 2005 the Department of Transportation made it mandatory for all new cars to be installed with a tire pressure monitoring system (TPMS). The TPMS system typically consists of transmitters in the tires and a receiver within the car. This project was the first in a series of projects designed to investigate the security vulnerabilities between a tire pressure monitoring sensor and the receiver within the car. Through controlled, distance, and roadside testing a generic receiver was designed using the universal software defined radio (USRP) and MATLAB for all TPMS variants

A Low-Power Wireless Multichannel Microsystem for Reliable Neural Recording.

This thesis reports on the development of a reliable, single-chip, multichannel wireless biotelemetry microsystem intended for extracellular neural recording from awake, mobile, and small animal models. The inherently conflicting requirements of low power and reliability are addressed in the proposed microsystem at architectural and circuit levels. Through employing the preliminary microsystems in various in-vivo experiments, the system requirements for reliable neural recording are identified and addressed at architectural level through the analytical tool: signal path co-optimization. The 2.85mm×3.84mm, mixed-signal ASIC integrates a low-noise front-end, programmable digital controller, an RF modulator, and an RF power amplifier (PA) at the ISM band of 433MHz on a single-chip; and is fabricated using a 0.5µm double-poly triple-metal n-well standard CMOS process. The proposed microsystem, incorporating the ASIC, is a 9-channel (8-neural, 1-audio) user programmable reliable wireless neural telemetry microsystem with a weight of 2.2g (including two 1.5V batteries) and size of 2.2×1.1×0.5cm3. The electrical characteristics of this microsystem are extensively characterized via benchtop tests. The transmitter consumes 5mW and has a measured total input referred voltage noise of 4.74µVrms, 6.47µVrms, and 8.27µVrms at transmission distances of 3m, 10m, and 20m, respectively. The measured inter-channel crosstalk is less than 3.5% and battery life is about an hour. To compare the wireless neural telemetry systems, a figure of merit (FoM) is defined as the reciprocal of the power spent on broadcasting one channel over one meter distance. The proposed microsystem’s FoM is an order of magnitude larger compared to all other research and commercial systems. The proposed biotelemetry system has been successfully used in two in-vivo neural recording experiments: i) from a freely roaming South-American cockroach, and ii) from an awake and mobile rat.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91542/1/aborna_1.pd

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

New Launch Methodologies for the Micro-Millennia

Rapid advancements in nano-technology have led to numerous improvements in microsatellite design. In the past twenty years, this class of satellites (10-100 kg mass) has repeatedly demonstrated their worth as vehicles for space science, technology demonstration, communications, remote sensing, education and information transfer. Within the past decade, the dramatic transition from experimentation to significant applications has prompted the implementation of numerous new launch methodologies. However, none have adequately met all the requirements stipulated by the small satellite market. The STARSAT launch vehicle has been tailored to specifically address the needs of the micro-satellite mission at a fraction of the cost of conventional launch systems. In addition, the predefined orbital parameters of these historically secondary payloads are no longer adequate for these mature and significant satellite missions. The implementation of the STARSAT design will enable low earth orbital insertion at any inclination without a corresponding increase in consumer cost. STARSAT will permit a wide array of scientific organizations, engineering corporations, universities, and even individuals, economically realistic access to space. The STARSAT launch system utilizes high altitude space balloons coupled with an optimized propulsion platform to initiate a high performance LEO (Low Earth Orbit) transfer maneuver from a stratospheric altitude of 20 to 25 kilometers. Lack of drag, near earth gravity, and high atmospheric pressures coupled with a heavy focus on reducing overall payload mass enables STARSAT to achieve high orbital altitudes with minimal propulsion requirements. Phase 1 of the STARSAT design, fabrication and launch underway at the Kennedy Space Center in Florida is led by the development teams of STARHUNTER Corporation in conjunction with the National Aeronautics and Space Administration, The Florida Space Institute and the Central Florida Remote Sensing Labs. This conceptual report details the STARSAT orbital insertion profile, as well as subsystem design with a focus on propulsion and guidance techniques. Telemetry from the maiden launch of STARSAT will be discussed, in addition to future design goals. Overall, STARSAT has resulted in a cost effective mission profile for use throughout the small satellite industry

An FPGA-based 77 GHzs RADAR signal processing system for automotive collision avoidance

An FPGA implementable Verilog HDL based signal processing algorithm has been developed to detect the range and velocity of target vehicles using a MEMS based 77 GHz LFMCW long range automotive radar. The algorithm generates a tuning voltage to control a GaAs based VCO to produce a triangular chirp signal, controls the operation of MEMS components, and finally processes the IF signal to determine the range and veolicty of the detected targets. The Verilog HDL code has been developed targeting the Xilinx Virtex-5 SX50T FPGA. The developed algorithm enables the MEMS radar to detect 24 targets in an optimum timespan of 6.42 ms in the range of 0.4 to 200 m with a range resolution of 0.19 m and a maximum range error 0.25 m. A maximum relative velocity of ±300 km/h can be determined with a velocity resolution in HDL of 0.95 m/s and a maximum velocity error of 0.83 m/s with a sweep duration of 1 ms