Link level performance evaluation and link abstraction for LTE/LTE-advanced downlink

Els objectius principals d'aquesta tesis són l'avaluació del rendiment a nivell d'enllaç i l'estudi de l'abstracció de l'enllaç pel LTE/LTE-Advanced DL. S’ha desenvolupat un simulador del nivell d'enllaç E-UTRA DL basat en la tecnologia MIMO-OFDM. Es simulen els errors d'estimació de canal amb un model d'error de soroll additiu Gaussià anomenat CEEM. El resultat d'aquest simulador serveix per avaluar el rendiment a nivell d'enllaç del LTE/LTE-Advanced DL en diferents entorns . La idea bàsica dels mètodes d'abstracció de l'enllaç és mapejar el vector de SNRs de les subportadores a un valor escalar, l'anomenada ESNR, la qual és usada per a predir la BLER. Proposem un innovador mètode d'abstracció de l'enllaç que pot predir la BLER amb bona precisió en esvaïments multicamí i que inclouen els efectes de les retransmissions HARQ. El mètode proposat es basa amb l'estimació de la informació mútua entre els bits transmesos i els LLRs rebuts.The main objectives of this dissertation are the evaluation of the link level performance and the study of link abstraction for LTE/LTE-Advanced DL. An E-UTRA DL link level simulator has been developed based on MIMO-OFDM technology. We simulate channel estimation errors by a Gaussian additive noise error model called CEEM. The result of this simulator serves to evaluate the MIMO-OFDM LTE/LTE-Advanced DL link level performance in different environments. The basic idea of link abstraction methods is to map the vector of the subcarrier SNRs to a single scalar, the ESNR, which is then used to predict the BLER. We propose a novel link abstraction method that can predict the BLER with good accuracy in multipath fading and including the effects of HARQ retransmissions. The proposed method is based on estimating the mutual information between the transmitted bits and the received LLRs.Postprint (published version

Signal Alignment: Enabling Physical Layer Network Coding for MIMO Networking

published_or_final_versio

A Novel Graph Neural Network-based Framework for Automatic Modulation Classification in Mobile Environments

Automatic modulation classification (AMC) refers to a signal processing procedure through which the modulation type and order of an observed signal are identified without any prior information about the communications setup. AMC has been recognized as one of the essential measures in various communications research fields such as intelligent modem design, spectrum sensing and management, and threat detection. The research literature in AMC is limited to accounting only for the noise that affects the received signal, which makes their models applicable for stationary environments. However, a more practical and real-world application of AMC can be found in mobile environments where a higher number of distorting effects is present. Hence, in this dissertation, we have developed a solution in which the distorting effects of mobile environments, e.g., multipath, Doppler shift, frequency, phase and timing offset, do not influence the process of identifying the modulation type and order classification. This solution has two major parts: recording an emulated dataset in mobile environments with real-world parameters (MIMOSigRef-SD), and developing an efficient feature-based AMC classifier. The latter itself includes two modules: feature extraction and classification. The feature extraction module runs upon a dynamic spatio-temporal graph convolutional neural network architecture, which tackles the challenges of statistical pattern recognition of received samples and assignment of constellation points. After organizing the feature space in the classification module, a support vector machine is adopted to be trained and perform classification operation. The designed robust feature extraction modules enable the developed solution to outperform other state-of-the-art AMC platforms in terms of classification accuracy and efficiency, which is an important factor for real-world implementations. We validated the performance of our developed solution in a prototyping and field-testing process in environments similar to MIMOSigRef-SD. Therefore, taking all aspects into consideration, our developed solution is deemed to be more practical and feasible for implementation in the next generations of communication systems. Advisor: Hamid R. Sharif-Kashan

Link abstraction models based on mutual information for LTE downlink

Postprint (author’s final draft

大規模システムLSI設計のための統一的ハードウェア・ソフトウェア協調検証手法

Currently, the complexity of embedded LSI system is growing faster than the productivity of system design. This trend results in a design productivity gap, particularly in tight development time. Since the verification task takes bigger part of development task, it becomes a major challenge in LSI system design. In order to guarantee system reliability and quality of results (QoR), verifying large coverage of system functionality requires huge amount of relevant test cases and various scenario of evaluations. To overcome these problems, verification methodology is evolving toward supporting higher level of design abstraction by employing HW-SW co-verification. In this study, we present a novel approach for verification LSI circuit which is called as unified HW/SW co-verification framework. The study aims to improve design efficiency while maintains implementation consistency in the point of view of system-level performance. The proposed data-driven simulation and flexible interface of HW and SW design become the backbone of verification framework. In order to avoid time consuming, prone error, and iterative design spin-off in a large team, the proposed framework has to support multiple design abstractions. Hence, it can close the loop of design, exploration, optimization, and testing. Furthermore, the proposed methodology is also able to co-operate with system-level simulation in high-level abstraction, which is easy to extend for various applications and enables fast-turn around design modification. These contributions are discussed in chapter 3. In order to show the effectiveness and the use-cases of the proposed verification framework, the evaluation and metrics assessments of Very High Throughput wireless LAN system design are carried out. Two application examples are provided. The first case in chapter 4 is intended for fast verification and design exploration of large circuit. The Maximum Likelihood Detection (MLD) MIMO decoder is considered as Design Under Test (DUT). The second case, as presented in chapter 5, is the evaluation for system-level simulation. The full transceiver system based on IEEE 802.11ac standard is employed as DUT. Experimental results show that the proposed verification approach gives significant improvements of verification time (e.g. up to 10,000 times) over the conventional scheme. The proposed framework is also able to support various schemes of system level evaluations and cross-layer evaluation of wireless system.九州工業大学博士学位論文 学位記番号：情工博甲第328号 学位授与年月日：平成29年6月30日1 Introduction|2 Design and Verification in LSI System Design|3 Unified HW/SW Co-verification Methodology|4 Fast Co-verification and Design Exploration in Complex Circuits|5 Unified System Level Simulator for Very High Throughput Wireless Systems|6 Conclusion and Future Work九州工業大学平成29年

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP