IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling ADC

This work presents IDDQ testing of a CMOS first order sigma-delta modulator of an 8-bit oversampling analog-to-digital converter using a built-in current sensor [BICS]. Gate-drain, source-drain, gate-source and gate-substrate bridging faults are injected using fault injection transistors. All the four faults cause varying fault currents and are successfully detected by the BICS at a good operation speed. The BICS have a negligible impact on the performance of the modulator and an external pin is provided to completely cut-off the BICS from the modulator. The modulator was designed and fabricated in 1.5 μm n-well CMOS process. The decimator was designed on Altera\u27s FLEXE20K board using Verilog. The modulator and decimator were assembled together to form a sigma-delta ADC

Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

An advanced Framework for efficient IC optimization based on analytical models engine

En base als reptes sorgits a conseqüència de l'escalat de la tecnologia, la present tesis desenvolupa i analitza un conjunt d'eines orientades a avaluar la sensibilitat a la propagació d'esdeveniments SET en circuits microelectrònics. S'han proposant varies mètriques de propagació de SETs considerant l'impacto dels emmascaraments lògic, elèctric i combinat lògic-elèctric. Aquestes mètriques proporcionen una via d'anàlisi per quantificar tant les regions més susceptibles a propagar SETs com les sortides més susceptibles de rebre'ls. S'ha desenvolupat un conjunt d'algorismes de cerca de camins sensibilitzables altament adaptables a múltiples aplicacions, un sistema lògic especific i diverses tècniques de simplificació de circuits. S'ha demostrat que el retard d'un camí donat depèn dels vectors de sensibilització aplicats a les portes que formen part del mateix, essent aquesta variació de retard comparable a la atribuïble a les variacions paramètriques del proces.En base a los desafíos surgidos a consecuencia del escalado de la tecnología, la presente tesis desarrolla y analiza un conjunto de herramientas orientadas a evaluar la sensibilidad a la propagación de eventos SET en circuitos microelectrónicos. Se han propuesto varias métricas de propagación de SETs considerando el impacto de los enmascaramientos lógico, eléctrico y combinado lógico-eléctrico. Estas métricas proporcionan una vía de análisis para cuantificar tanto las regiones más susceptibles a propagar eventos SET como las salidas más susceptibles a recibirlos. Ha sido desarrollado un conjunto de algoritmos de búsqueda de caminos sensibilizables altamente adaptables a múltiples aplicaciones, un sistema lógico especifico y diversas técnicas de simplificación de circuitos. Se ha demostrado que el retardo de un camino dado depende de los vectores de sensibilización aplicados a las puertas que forman parte del mismo, siendo esta variación de retardo comparable a la atribuible a las variaciones paramétricas del proceso.Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variation

Design and implementation of synchronous buck converter based PV energy system for battery charging applications

The Photo Voltaic (PV) energy system is a very new concept in use, which is gaining popularity due to increasing importance to research on alternative sources of energy over depletion of the conventional fossil fuels world-wide. The systems are being developed to extract energy from the sun in the most efficient manner and suit them to the available loads without affecting their performance. In this project, synchronous buck converter based PV energy system for portable applications; especially low power device applications such as charging mobile phone batteries are considered. Here, the converter topology used uses soft switching technique to reduce the switching losses which is found prominently in the conventional buck converter, thus efficiency of the system is improved and the heating of MOSFETs due to switching losses reduce and the MOSFETs have a longer life. The DC power extracted from the PV array is synthesized and modulated by the converter to suit the load requirements. Further, the comparative study between the proposed synchronous buck converter and the conventional buck converter is analysed in terms of efficiency improvement and switching loss reduction. The proposed system is simulated in the MATLAB-Simulink environment and the practical implementation of the proposed converter is done to validate the theoretical results. Open-loop control of synchronous buck converter based PV energy system is realised through ICs and experimental results were observed

Advancement on the Susceptibility of Analog Front-Ends to EMI

L'abstract è presente nell'allegato / the abstract is in the attachmen

AUTOMATIC TEST GENERATION BASED ON CONSTRAINTS

It seems to be a very hard task to enhance the properties of widespreadly used automatic test pattern generation algorithms. Experiences show that achievements are sometimes not worth the effort. In the authors' opinion this fact stems from the basically 'algorithm oriented' nature of research made in the past. A new experimental framework is presented for the problem, considering network representation and search control algorithms as equally important parts. The network is represented by object- oriented data-flow networks, the search control algorithm is based on constraint satisfaction, and a special kind of dependency directed backtracking which we call constraint slackening. Similar methods were proved to be very useful in automatic system diagnosis by DAVIS (1985) and others, although have not been introduced to testing yet. This paper summarises the basic notions of constraint satisfaction, the potential advantages of using it for building test generation systems, and shows implementational details of a test generation system, based on constraints. Experiences of the run-time tests show that constraint-based test generation can be highly efficient

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

A Novel Nonlinear Mason Model And Nonlinear Distortion Characterization For Surface Acoustic Wave Duplexers

Surface acoustic wave (SAW) technology has been in use for well over one century. In the last few decades, due to its low cost and high performance, this technology has been widely adopted in modern wireless communication systems, to build filtering devices at radio frequency (RF). SAW filters and duplexers can be virtually found inside every mobile handset. SAW devices are traditionally recognized as passive devices with high linear signal processing behavior. However, recent deployments of third generation (3G) and fourth generation (4G) mobile networks require the handsets to handle an increasing number of frequency bands with more complex modulation /demodulation schemes and higher data rate for more subscribers. These requirements directly demand more stringent linearity specifications on the front end devices, including the SAW duplexers. In the past, SAW duplexer design was based on empirically obtained design rules to meet the linearity specifications. Lack of predictability and an understanding of the root cause of the nonlinearity have limited the potential applications of SAW duplexers. Therefore, research on the nonlinearity characterization and an accurate modeling of SAW nonlinearity for mobile device applications are very much needed. The Ph.D. work presented here primarily focuses on developing a general nonlinear model for SAW resonators/duplexers. Their nonlinear characteristics were investigated by measuring the harmonic and intermodulation distortions of resonators. A nonlinear Mason model is developed and the characterization results are integrated into SAW duplexer design flows to help to simulate the nonlinear effects accurately and improve the linearity performance of the products. iv In this dissertation, first, a novel nonlinear Mason equivalent circuit model including a third order nonlinear coefficient in the wave propagation is presented. Next, the nonlinear distortions of SAW resonators are analyzed by measuring large-signal harmonic and intermodulation spurious emission on resonators using a wafer probe station. The influence of the setups on the measurement reliability and reproducibility is discussed. Further, the nonlinear Mason model is validated by comparing its simulation results with harmonic and intermodulation measurements on SAW resonators and a WCDMA Band 5 duplexer. The Mason model developed and presented here is the first and only nonlinear physical model for SAW devices based on the equivalent circuit approach. By using this new model, good simulation measurement agreements are obtained on both harmonic and intermodulation distortions for SAW resonators and duplexers. These outcomes demonstrate the validity of the research on both the characterization and modeling of SAW devices. The result obtained confirms that the assumption of the representation of the 3 rd order nonlinearity in the propagation by a single coefficient is vali

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient