INTRODUCING AN OPTIMAL QCA CROSSBAR SWITCH FOR BASELINE NETWORK

Crossbar switch is the basic component in multi-stage interconnection networks. Therefore, this study was conducted to investigate performance of a crossbar switch with two multiplexers. The presented crossbar switch was simulated using quantum-dot cellular automata (QCA) technology and QCA Designer software, and was studied and optimized in terms of cell number, occupied area, number of clocks, and energy consumption. Using the provided crossbar switch, the baseline network was designed to be optimal in terms of cell number and occupied area. Also, the number of input states was investigated and simulated to verify accuracy of the baseline network. The proposed crossbar switch uses 62 QCA cells and the occupied area by the switch is equal to 0.06µm2 and its latency equals 4 clock zones, which is more efficient than the other designs. In this paper, using the presented crossbar switch, the baseline network was designed with 1713 cells, and occupied area of 2.89µm2

Design and Simulation of an Efficient Quaternary Full-Adder Based on Carbon Nanotube Field Effect Transistor

The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. In this paper, an efficient quaternary full-adder based on CNTFET technology is presented which consists of two half adder blocks, a quaternary decoder and a carry generator circuit. In the proposed architecture, the base-two and base-four circuit design techniques are combined to take the full advantages of both techniques namely simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using the Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure utilizing a supply voltage of 0.9 volts, reveals the power consumption, propagation delay and energy index equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively

Logic Synthesis for Established and Emerging Computing

Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported

A Practical Hardware Implementation of Systemic Computation

It is widely accepted that natural computation, such as brain computation, is far superior to typical computational approaches addressing tasks such as learning and parallel processing. As conventional silicon-based technologies are about to reach their physical limits, researchers have drawn inspiration from nature to found new computational paradigms. Such a newly-conceived paradigm is Systemic Computation (SC). SC is a bio-inspired model of computation. It incorporates natural characteristics and defines a massively parallel non-von Neumann computer architecture that can model natural systems efficiently. This thesis investigates the viability and utility of a Systemic Computation hardware implementation, since prior software-based approaches have proved inadequate in terms of performance and flexibility. This is achieved by addressing three main research challenges regarding the level of support for the natural properties of SC, the design of its implied architecture and methods to make the implementation practical and efficient. Various hardware-based approaches to Natural Computation are reviewed and their compatibility and suitability, with respect to the SC paradigm, is investigated. FPGAs are identified as the most appropriate implementation platform through critical evaluation and the first prototype Hardware Architecture of Systemic computation (HAoS) is presented. HAoS is a novel custom digital design, which takes advantage of the inbuilt parallelism of an FPGA and the highly efficient matching capability of a Ternary Content Addressable Memory. It provides basic processing capabilities in order to minimize time-demanding data transfers, while the optional use of a CPU provides high-level processing support. It is optimized and extended to a practical hardware platform accompanied by a software framework to provide an efficient SC programming solution. The suggested platform is evaluated using three bio-inspired models and analysis shows that it satisfies the research challenges and provides an effective solution in terms of efficiency versus flexibility trade-off

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

Laboratory-directed research and development: FY 1996 progress report

This report summarizes the FY 1996 goals and accomplishments of Laboratory-Directed Research and Development (LDRD) projects. It gives an overview of the LDRD program, summarizes work done on individual research projects, and provides an index to the projects` principal investigators. Projects are grouped by their LDRD component: Individual Projects, Competency Development, and Program Development. Within each component, they are further divided into nine technical disciplines: (1) materials science, (2) engineering and base technologies, (3) plasmas, fluids, and particle beams, (4) chemistry, (5) mathematics and computational sciences, (6) atomic and molecular physics, (7) geoscience, space science, and astrophysics, (8) nuclear and particle physics, and (9) biosciences