Performance Comparison of Terrestrial DVB Detection using LDPC and Turbo Codes

Last-generation and future wireless communication standards, such as DVB-T2 or DVB-NGH, are including multi-antenna transmission and reception in order to increase bandwidth efficiency and receiver robustness. The main goal is to combine diversity and spatial multiplexing in order to fully exploit the multiple-input multiple output (MIMO) channel capacity. Full-rate full-diversity (FRFD) space-time codes (STC) such as the Golden code are studied for that purpose. However, despite their larger achievable capacity, most of them present high complexity for soft detection, which hinders their combination with soft-input decoders in bit-interleaved coded modulation (BICM) schemes. This article presents a low complexity soft detection algorithm for the reception of FRFD space-frequency block codes in BICM orthogonal frequency division multiplexing (OFDM) systems and gives the performance comparision using Ldpc and Turbo codes. The proposed detector maintains a reduced and fixed complexity, avoiding the variable nature of the list sphere decoder (LSD) due to its dependence on the noise and channel conditions. Complexity and simulation based performance results are provided which show that the proposed detector performs close to the optimal log-maximum a posteriori (MAP) detection in a variety of DVB-T2 broadcasting scenarios

Multi-carrier transmission techniques toward flexible and efficient wireless communication systems

制度:新 ; 文部省報告番号:甲2562号 ; 学位の種類:博士(国際情報通信学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新470

Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems

In this paper, implementation of a detector with parallel partial candidate-search algorithm is described. Two fully independent partial candidate search processes are simultaneously employed for two groups of transmit antennas based on QR decomposition (QRD) and QL decomposition (QLD) of a multiple-input multiple-output (MIMO) channel matrix. By using separate simultaneous candidate searching processes, the proposed implementation of QRD-QLD searching-based sphere detector provides a smaller latency and a lower computational complexity than the original QRD-M detector for similar error-rate performance in wireless communications systems employing four transmit and four receive antennas with 16-QAM or 64-QAM constellation size. It is shown that in coded MIMO orthogonal frequency division multiplexing (MIMO OFDM) systems, the detection latency and computational complexity of a receiver can be substantially reduced by using the proposed QRD-QLD detector implementation. The QRD-QLD-based sphere detector is also implemented using Field Programmable Gate Array (FPGA) and application specific integrated circuit (ASIC), and its hardware design complexity is compared with that of other sphere detectors reported in the literature.Nokia Renesas MobileTexas InstrumentsXilinxNational Science Foundatio

Novel LDPC coding and decoding strategies: design, analysis, and algorithms

In this digital era, modern communication systems play an essential part in nearly every aspect of life, with examples ranging from mobile networks and satellite communications to Internet and data transfer. Unfortunately, all communication systems in a practical setting are noisy, which indicates that we can either improve the physical characteristics of the channel or find a possible systematical solution, i.e. error control coding. The history of error control coding dates back to 1948 when Claude Shannon published his celebrated work “A Mathematical Theory of Communication”, which built a framework for channel coding, source coding and information theory. For the first time, we saw evidence for the existence of channel codes, which enable reliable communication as long as the information rate of the code does not surpass the so-called channel capacity. Nevertheless, in the following 60 years none of the codes have been proven closely to approach the theoretical bound until the arrival of turbo codes and the renaissance of LDPC codes. As a strong contender of turbo codes, the advantages of LDPC codes include parallel implementation of decoding algorithms and, more crucially, graphical construction of codes. However, there are also some drawbacks to LDPC codes, e.g. significant performance degradation due to the presence of short cycles or very high decoding latency. In this thesis, we will focus on the practical realisation of finite-length LDPC codes and devise algorithms to tackle those issues. Firstly, rate-compatible (RC) LDPC codes with short/moderate block lengths are investigated on the basis of optimising the graphical structure of the tanner graph (TG), in order to achieve a variety of code rates (0.1 < R < 0.9) by only using a single encoder-decoder pair. As is widely recognised in the literature, the presence of short cycles considerably reduces the overall performance of LDPC codes which significantly limits their application in communication systems. To reduce the impact of short cycles effectively for different code rates, algorithms for counting short cycles and a graph-related metric called Extrinsic Message Degree (EMD) are applied with the development of the proposed puncturing and extension techniques. A complete set of simulations are carried out to demonstrate that the proposed RC designs can largely minimise the performance loss caused by puncturing or extension. Secondly, at the decoding end, we study novel decoding strategies which compensate for the negative effect of short cycles by reweighting part of the extrinsic messages exchanged between the nodes of a TG. The proposed reweighted belief propagation (BP) algorithms aim to implement efficient decoding, i.e. accurate signal reconstruction and low decoding latency, for LDPC codes via various design methods. A variable factor appearance probability belief propagation (VFAP-BP) algorithm is proposed along with an improved version called a locally-optimized reweighted (LOW)-BP algorithm, both of which can be employed to enhance decoding performance significantly for regular and irregular LDPC codes. More importantly, the optimisation of reweighting parameters only takes place in an offline stage so that no additional computational complexity is required during the real-time decoding process. Lastly, two iterative detection and decoding (IDD) receivers are presented for multiple-input multiple-output (MIMO) systems operating in a spatial multiplexing configuration. QR decomposition (QRD)-type IDD receivers utilise the proposed multiple-feedback (MF)-QRD or variable-M (VM)-QRD detection algorithm with a standard BP decoding algorithm, while knowledge-aided (KA)-type receivers are equipped with a simple soft parallel interference cancellation (PIC) detector and the proposed reweighted BP decoders. In the uncoded scenario, the proposed MF-QRD and VM-QRD algorithms are shown to approach optimal performance, yet require a reduced computational complexity. In the LDPC-coded scenario, simulation results have illustrated that the proposed QRD-type IDD receivers can offer near-optimal performance after a small number of detection/decoding iterations and the proposed KA-type IDD receivers significantly outperform receivers using alternative decoding algorithms, while requiring similar decoding complexity

Cooperative Partial Detection for MIMO Relay Networks

This paper was submitted by the author prior to final official version. For official version please see http://hdl.handle.net/1911/64372Cooperative communication has recently re-emerged as a possible paradigm shift to realize the promises of the ever increasing wireless communication market; how- ever, there have been few, if any, studies to translate theoretical results into feasi- ble schemes with their particular practical challenges. The multiple-input multiple- output (MIMO) technique is another method that has been recently employed in different standards and protocols, often as an optional scenario, to further improve the reliability and data rate of different wireless communication applications. In this work, we look into possible methods and algorithms for combining these two tech- niques to take advantage of the benefits of both. In this thesis, we will consider methods that consider the limitations of practical solutions, which, to the best of our knowledge, are the first time to be considered in this context. We will present complexity reduction techniques for MIMO systems in cooperative systems. Furthermore, we will present architectures for flexible and configurable MIMO detectors. These architectures could support a range of data rates, modulation orders and numbers of antennas, and therefore, are crucial in the different nodes of cooperative systems. The breadth-first search employed in our realization presents a large opportunity to exploit the parallelism of the FPGA in order to achieve high data rates. Algorithmic modifications to address potential sequential bottlenecks in the traditional bread-first search-based SD are highlighted in the thesis. We will present a novel Cooperative Partial Detection (CPD) approach in MIMO relay channels, where instead of applying the conventional full detection in the relay, the relay performs a partial detection and forwards the detected parts of the message to the destination. We will demonstrate how this approach leads to controlling the complexity in the relay and helping it choose how much it is willing to cooperate based on its available resources. We will discuss the complexity implications of this method, and more importantly, present hardware verification and over-the-air experimentation of CPD using the Wireless Open-access Research Platform (WARP).NSF grants EIA-0321266, CCF-0541363, CNS-0551692, CNS-0619767, EECS-0925942, and CNS-0923479, Nokia, Xilinx, Nokia Siemens Networks, Texas Instruments, and Azimuth Systems

Interleaved frequency Division Multiple Access with Multiple Antennas and Block spreading for Mobile Broadband Communications

Ph.DDOCTOR OF PHILOSOPH

Implementación VLSI del algoritmo de proyecciones sucesivas para detección de sistemas MIMO

[EN] The insatiable demand for bandwidth of communication on the part of end-users, linked to the lowering the price of the terminals and in telecommunication services have led to a spectacular growth of the wireless communications market in recent years. Those entities that are responsible, at the international level, of the technological standardization have known to guide this growth writing standards as LTE (Long Term Evolution), IEEE 802.11 (WiFi) and IEEE 802.16 (WiMax) or 3G networks or 4GPP. They all share a common denominator, for the improvement of the spectral efficiency, the use of MIMO technologies, which uses multiple antennas on transmitter and receiver, and the use of high modulation schemes as 256QAM, introduced in revision 12 of the standard 3GPP-LTE. Under this perspective of great gains in the spectral efficiency, it is not surprising that MIMO technology has been incorporated into the standards mentioned above. However, achieving these gains is not trivial, to the extent that the VLSI implementation of this technology has become a challenge. In this thesis has undertaken a comprehensive study of different MIMO detectors, studying those belonging to the two families that show best features for being implemented in VLSI technology: successive interference cancellation (VBLAST detector) and based on a search in tree (KBest detector). Although initially the benefits achieved by the seconds (KBest) are far superior to those of the first (VBLAST), the recent appearance in the specialized literature of the Successive Projections Algorithm (SPA) opens the door to the development of a new detector, belonging to the family of the detectors of Successive Interference Cancellations (SIC), which will be able to compete in performance with the KBest detectors. This work provides the necessary algorithmic keys that make viable and competitive the hardware implementation of the SPA algorithm. In particular, two mechanisms of control of repetitions have been developed: Simplified-ESPA (SESPA) and Table-ESPA (TESPA), and the mechanisms for obtaining hard and soft output, existing in the literature, have been adapted to this algorithm. It has designed the first VLSI architecture for the SPA algorithm, being highly flexible, in the sense that adapts to different conditions of transmission and complies with the latest published specifications in the WiMAX and LTE standards. The flexibility of the architecture allows you to select different configurations of antennas in transmission and reception, from 2x2 to 4x4, different modulation schemes from QPSK until 256QAM, controls the balance between transmission rate and the benefits BER/FER and offers the soft output and hard output decisions. Finally, with this architecture has been implemented the SESPA and TESPA detectors, with soft output and hard output, in FPGA and ASIC technology. These detectors have been evaluated and compared to the best published in the specialized literature, achieving a peak rate of 465 Mbps for the detector SESPA 4x4 256QAM, with an area of 3.83 mm2 with a 90 nm technology. The detectors implemented offer as added value, in addition to the high configurability, the ability to decode 256-QAM without increasing the area. This feature is highly competitive with the non-linear detectors based on KBest, which are very sensitive, in regard to decoding rate and area, with the selected modulation scheme. In addition, the detectors based on ESPA reach a FER performance (soft output) clearly competitive with KBest detectors, due to a higher quality of the LLR generated by the ESPA. The comparison with other flexible architectures selected shows that the SESPA and TESPA detectors offer the greater configurability of transmission parameters and the best balance between area, BER performance and detection rate.[ES] La insaciable demanda de ancho de banda de comunicación por parte de los usuarios finales, unido al abaratamiento de los terminales y de los servicios de telecomunicación han provocado un crecimiento espectacular del mercado de las comunicaciones inalámbricas en estos últimos años. Las entidades responsables, a nivel internacional, de la estandarización tecnológica han sabido acompañar y guiar este crecimiento redactando normas como LTE (Long Term Evolution), IEEE 802.11 (WiFi) e IEEE 802.16 (WiMax) o las redes 3G o 4GPP. Todas ellas comparten como denominador común, para la mejora de la eficiencia espectral, el uso de las tecnologías MIMO, que utiliza múltiples antenas en emisor y receptor, y el uso de esquemas de modulación elevados como 256QAM, introducido en la revisión 12 del estándar 3GPP-LTE. Bajo esta perspectiva de grandes ganancias en la eficiencia espectral, no es de extrañar que la tecnología MIMO haya sido incorporada en los estándares mencionados anteriormente. No obstante, conseguir estas ganancias no es trivial, hasta el punto de que la implementación VLSI de esta tecnología se ha convertido en un reto. En esta tesis se ha realizado un estudio exhaustivo de diferentes detectores MIMO, fijando el punto de mira en aquellos pertenecientes a las dos familias que muestran mejores características para su implementación VLSI: cancelación sucesiva de interferencias (detector VBLAST) y basados en búsqueda en árbol (detector KBest). Aunque inicialmente las prestaciones alcanzadas por los segundos (KBest) son muy superiores a las de los primeros (VBLAST), la reciente aparición en la literatura especializada del algoritmo de proyecciones sucesivas (SPA) abre la puerta al desarrollo de un nuevo detector, que pueda competir en prestaciones con los detectores KBest. La tesis aporta las claves algorítmicas necesarias que hacen viable y competitiva la implementación hardware del algoritmo SPA. En particular, se han desarrollado dos mecanismos de control de repeticiones: Simplified-ESPA (SESPA) y Table-ESPA (TESPA), y se han adaptado los mecanismos de obtención de salidas hard output y soft output, existentes en la literatura, a este algoritmo. Se ha diseñado la primera arquitectura VLSI para el algoritmo SPA, siendo ésta altamente flexible, en el sentido de que se adapta a diferentes condiciones de transmisión y cumple con las últimas especificaciones publicadas en los estándares WiMAX y LTE. La flexibilidad de la arquitectura permite seleccionar diferentes configuraciones de antenas en transmisión y recepción, desde 2x2 hasta 4x4, diferentes esquemas de modulación desde QPSK hasta 256QAM, controla el balance entre tasa de transmisión y las prestaciones BER/FER y ofrece las decisiones soft output y hard output. Finalmente, con esta arquitectura se ha realizado la implementación de los detectores SESPA y TESPA, con salidas soft output y hard output, en los dispositivos FPGA y ASIC. Estos detectores han sido evaluados y comparados con los mejores publicados en la literatura especializada, consiguiendo la tasa de pico máxima de 465 Mbps para el detector SESPA 4x4 256QAM, en un área de 3.83 mm2 con una tecnología de 90 nm. Los detectores implementados ofrecen como valor añadido, además de la alta configurabilidad, la posibilidad de decodificar 256QAM sin incrementar el área. Esta característica es altamente competitiva con los detectores no lineales basados en KBest, que son muy sensibles, en cuanto a tasa de decodificación y área se refiere, con el esquema de modulación seleccionado. Además, los detectores basados en ESPA alcanzan unas prestaciones FER (soft output) claramente competitivas con los detectores KBest, debido a la mayor calidad del LLR generado por el ESPA. La comparación con otras arquitecturas flexibles seleccionadas demuestra que los detectores SESPA y TESPA ofrecen la mayor configurabilidad de parámetros de transmisión y el mejor equilibrio entre área, pr[CA] La insaciable demanda d'ample de banda de comunicació per part dels usuaris finals, unit a l'abaratiment dels terminals i dels servicis de telecomunicació han provocat un creixement espectacular del mercat de les comunicacions sense fils en aquests últims anys. Les entitats responsables, a nivell internacional, de l'estandardització tecnològica han sabut acompanyar i guiar aquest creixement redactant normes com LTE (Long Term Evolution), IEEE 802.11 (WiFi) i IEEE 802.16 (WiMax) o les xarxes 3G o 4GPP. Totes elles comparteixen com denominador comú, per a la millora de l'eficiència espectral, l'ús de les tecnologies MIMO, que utilitza múltiples antenes en emissor i receptor, i l'ús d'esquemes de modulació elevats com 256QAM, introduït en la revisió 12 de l'estàndard 3GPP-LTE. Baix esta perspectiva de grans guanys en l'eficiència espectral, no és d'estranyar que la tecnologia MIMO hi haja estat incorporada en els normatives mencionats anteriorment. No obstant això, aconseguir aquests guanys no és trivial, fins l'extrem que la implementació VLSI d'aquesta tecnologia s'ha convertit en un repte. En aquesta tesi s'ha realitzat un estudi exhaustiu de diferents detectors MIMO, fixant el punt de mira en aquells que pertanyen a les dos famílies que mostren millors característiques per a la seua implementació VLSI: cancel-lació successiva d'interferències (detector VBLAST) i els basats en recerca en arbre (detector KBest). Encara que inicialment les prestacions aconseguides pels segons (KBest) són molt superiors a les dels primers (VBLAST), la recent aparició en la literatura especialitzada de l'algoritme de projeccions successives (SPA) permet el desenvolupament d'un nou detector, que puga competir en prestacions amb els detectors KBest. Este treball aporta les claus algorítmiques necessàries que fan viable i competitiva la implementació hardware de l'algoritme SPA. En particular, s'han desenvolupat dos mecanismes de control de repeticions: Simplified-ESPA (SESPA) i Table-ESPA (TESPA), i s'han adaptat els mecanismes d'obtenció d'eixides hard-output i soft-output, existents en la literatura, a aquest algoritme. S'ha dissenyat la primera arquitectura VLSI per a l'algoritme SPA, sent aquesta altament flexible, en el sentit de que s'adapta a diferents condicions de transmissió i acompleix les últimes especificacions publicades en els estàndards WiMax i LTE. La flexibilitat de l'arquitectura permet seleccionar diferents configuracions d'antenes en transmissió i recepció, des de 2x2 fins 4x4, diferents esquemes de modulació des de QPSK fins 256QAM, controla el balanç entre taxa de transmissió i les prestacions BER/FER i ofereix les decisions hard output i soft output. Finalment, amb l'arquitectura proposta s'ha realitzat la implementació dels detectors SESPA i TESPA, amb eixides hard output i soft output, en els dispositius FPGA i en ASIC. Aquests detectors han segut valorats i comparats amb els millors publicats en la literatura especialitzada, i s'ha aconseguint la taxa de pic màxim de 465 Mbps per al detector SESPA 4x4 256QAM, dins una àrea de 3.83 mm2 en una tecnologia de 90 nm. Els detectors implementats ofereixen com a valor afegit, a més de l'alta configurabilitat, la possibilitat de decodificar 256QAM sense incrementar l'àrea. Esta característica és altament competitiva en els detectors no lineals basats en KBest, que són molt sensibles, en relació a taxa de decodificació i a l'àrea del circuit, a l'esquema de modulació seleccionada. A més a més, els detectors basats en ESPA aconsegueixen unes prestacions FER (soft output) clarament competitives amb els detectors KBEST, degut a la major qualitat del LLR generat per l'ESPA. La comparació amb altres arquitectures flexibles seleccionades demostra que els detectors SESPA i TESPA ofereixen una major configurabilitat de paràmetres de transmissió i un millor equilibri entre l'àrea del circuit, les prestacions BER i la taxa de deteMarín-Roig Ramón, J. (2016). Implementación VLSI del algoritmo de proyecciones sucesivas para detección de sistemas MIMO [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/62164TESI