A Novel Method to Improve the Test Efficiency of VLSI Tests

This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas

A Family of Controllable Cellular Automata for Pseudorandom Number Generation

In this paper, we present a family of novel Pseudorandom Number Generators (PRNGs) based on Controllable Cellular Automata (CCA) ─ CCA0, CCA1, CCA2 (NCA), CCA3 (BCA), CCA4 (asymmetric NCA), CCA5, CCA6 and CCA7 PRNGs. The ENT and DIEHARD test suites are used to evaluate the randomness of these CCA PRNGs. The results show that their randomness is better than that of conventional CA and PCA PRNGs while they do not lose the structure simplicity of 1-d CA. Moreover, their randomness can be comparable to that of 2-d CA PRNGs. Furthermore, we integrate six different types of CCA PRNGs to form CCA PRNG groups to see if the randomness quality of such groups could exceed that of any individual CCA PRNG. Genetic Algorithm (GA) is used to evolve the configuration of the CCA PRNG groups. Randomness test results on the evolved CCA PRNG groups show that the randomness of the evolved groups is further improved compared with any individual CCA PRNG

Characterisation of Hybrid Pixel Detectors with capacitive charge division

In order to fully exploit the physics potential of the future high energy e+ e- linear collider, a Vertex Tracker providing high resolution track reconstruction is required. Hybrid pixel sensors are an attractive technology due to their fast read-out capabilities and radiation hardness. A novel pixel detector layout with interleaved cells between the readout nodes has been developed to improve the single point resolution. The results of the characterisation of the first processed prototypes are reported.Comment: 5 pages, 2 figures, presented at LCWS2000, Linear Collider Workshop, October 24-28 2000, Fermi National Accelerator Laboratory, Batavia, Illinois, U.S.A. Proceedings to be published by the American Institute of Physic

Dynamic Virtual Page-based Flash Translation Layer with Novel Hot Data Identification and Adaptive Parallelism Management

Solid-state disks (SSDs) tend to replace traditional motor-driven hard disks in high-end storage devices in past few decades. However, various inherent features, such as out-of-place update [resorting to garbage collection (GC)] and limited endurance (resorting to wear leveling), need to be reduced to a large extent before that day comes. Both the GC and wear leveling fundamentally depend on hot data identification (HDI). In this paper, we propose a hot data-aware flash translation layer architecture based on a dynamic virtual page (DVPFTL) so as to improve the performance and lifetime of NAND flash devices. First, we develop a generalized dual layer HDI (DL-HDI) framework, which is composed of a cold data pre-classifier and a hot data post-identifier. Those can efficiently follow the frequency and recency of information access. Then, we design an adaptive parallelism manager (APM) to assign the clustered data chunks to distinct resident blocks in the SSD so as to prolong its endurance. Finally, the experimental results from our realized SSD prototype indicate that the DVPFTL scheme has reliably improved the parallelizability and endurance of NAND flash devices with improved GC-costs, compared with related works.Peer reviewe

An Evolutionary Approach to the Design of Controllable Cellular Automata Structure for Random Number Generation

Cellular Automata (CA) has been used in pseudorandom number generation over a decade. Recent studies show that two-dimensional (2-d) CA Pseudorandom Number Generators (PRNGs) may generate better random sequences than conventional one-dimensional (1-d) CA PRNGs, but they are more complex to implement in hardware than 1-d CA PRNGs. In this paper, we propose a new class of 1-d CA Controllable Cellular Automata (CCA) without much deviation from the structure simplicity of conventional 1-d CA. We give a general definition of CCA first and then introduce two types of CCA – CCA0 and CCA2. Our initial study on them shows that these two CCA PRNGs have better randomness quality than conventional 1-d CA PRNGs but their randomness is affected by their structures. To find good CCA0/CCA2 structures for pseudorandom number generation, we evolve them using the Evolutionary Multi-Objective Optimization (EMOO) techniques. Three different algorithms are presented in this paper. One makes use of an aggregation function; the other two are based on the Vector Evaluated Genetic Algorithm (VEGA). Evolution results show that these three algorithms all perform well. Applying a set of randomness tests on the evolved CCA PRNGs, we demonstrate that their randomness is better than that of 1-d CA PRNGs and can be comparable to that of two-dimensional CA PRNGs

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

The authors propose two fault-tolerance techniques for hybrid CMOS/nanoarchitecture implementing logic functions as look-up tables. The authors compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, the authors implement a combined two-dimensional coding scheme using Hamming and Bose-Chaudhuri-Hocquenghem (BCH) codes to address fault rates greater than 5. In the second technique, Hamming coding is complemented with bad line exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20). The authors have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don-t Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain