Computing centroids in current-mode technique

A novel current-mode circuit for calculating the centre of mass of a discrete distribution of currents is described. It is simple and compact, an ideal building block for VLSI analogue IC design. The design principles are presented as well as the simulated behaviour of a one-dimensional implementation

A 1.6 Gb/s, 3 mW CMOS receiver for optical communication

A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11 μA input, dissipates 3 mW of power, occupies 80 μm x 50 μm of area and operates at over 1.6 Gb/s

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL

Dynamic calibration of current-steering DAC

The demand for high-speed communication systems has dramatically increased during the last decades. Working as an interface between the digital and analog world, Digital-to-Analog converters (DACs) are becoming more and more important because they are a key part which limits the accuracy and speed of an overall system. Consequently, the requirements for high-speed and high-accuracy DACs are increasingly demanding. It is well recognized that dynamic performance of the DACs degrades dramatically with increasing input signal frequencies and update rates. The dynamic performance is often characterized by the spurious free dynamic range (SFDR). The SFDR is determined by the spectral harmonics, which are attributable to system nonlinearities.;A new calibration approach is presented in this thesis that compensates for the dynamic errors in performance. In this approach, the nonlinear components of the input dependent and previous input code dependent errors are characterized, and correction codes that can be used to calibrate the DAC for these nonlinearities are stored in a two-dimensional error look-up table. A series of pulses is generated at run time by addressing the error look-up table with the most significant bits of the Boolean input and by using the corresponding output to drive a calibration DAC whose output is summed with the original DAC output. The approach is applied at both the behavioral level and the circuit level in current-steering DAC.;The validity of this approach is verified by simulation. These simulations show that the dynamic nonlinearities can be dramatically reduced with this calibration scheme. The simulation results also show that this calibration approach is robust to errors in both the width and height of calibration pulses.;Experimental measurement results are also provided for a special case of this dynamic calibration algorithm that show that the dynamic performance can be improved through dynamic calibration, provided the mean error values in the table are close to their real values

A Current-Mode Multi-Channel Integrating Analog-to-Digital Converter

Multi-channel analog to digital converters (ADCs) are required where signals from multiple sensors can be digitized. A lower power per channel for such systems is important in order that when the number of channels is increased the power does not increase drastically. Many applications require signals from current output sensors, such as photosensors and photodiodes to be digitized. Applications for these sensors include spectroscopy and imaging. The ability to digitize current signals without converting currents to voltages saves power, area, and the design time required to implement I-to-V converters. This work describes a novel and unique current-mode multi-channel integrating ADC which processes current signals from sensors and converts it to digital format. The ADC facilitates the processing of current analog signals without the use of transconductors. An attempt has been made also to incorporate voltage-mode techniques into the current-mode design so that the advantages of both techniques can be utilized to augment the performance of the system. Additionally since input signals are in the form of currents, the dynamic range of the ADC is less dependant on the supply voltage. A prototype 4-channel ADC design was fabricated in a 0.5-micron bulk CMOS process. The measurement results for a 10Ksps sampling rate include a DNL, which is less than 0.5 LSB, and a power consumption of less than 2mW per channel