Design of Highly Efficient Analog-To-Digital Converters

The demand of higher data rates in communication systems is reflected in the constant evolution of communication standards. LTE-A and WiFi 802.11ac promote the use of carrier aggregation to increase the data rate of a wireless receiver. Recent DTV receivers promote the concept of full band capture to avoid the implementation of complex analog operations such as: filtering, equalization, modulation/demodulation, etc. All these operations can be implemented in a robust manner in the digital domain. Analog-to-Digital Converters (ADCs) are located at the heart of such architectures and require to have larger bandwidths and higher dynamic ranges. However, at higher data rates the power efficiency of ADCs tends to degrade. Moreover, while the scale of channel length in CMOS devices directly benefits the power, speed and area of digital circuits, analog circuits suffer from lower intrinsic gain and higher device mismatch. Thus, it has been difficult to design high-speed ADCs with low-power operation using traditional architectures without relying on increasingly complex digital calibration algorithms. This research presents three ADCs that introduce novel architectures to relax the specifications of the analog circuits and reduce the complexity of the digital calibration algorithms. A low-pass sigma delta ADC with 15 MHz of bandwidth is introduced. The system uses a low-power 7-bit quantizer from which the four most significant bits are used for the operation of the sigma delta ADC. The remaining three least significant bits are used for the realization of a frequency domain algorithm for quantization noise improvement. The prototype was implemented in 130 nm CMOS technology. For this prototype, the use of the 7-bit quantizer and algorithm improved the SNDR from 69 dB to 75 dB. The obtained FoM was 145 fJ/conversion-step. In a second project, the problem of high power consumption demanded from closed loop operational amplifiers operating at Giga hertz frequency is addressed. Especially the dependency of the power consumption to the closed loop gain. This project presents a low-pass sigma delta ADC with 75 MHz bandwidth. The traditional summing amplifier used for excess loop compensation delay is substituted by a summing amplifier with current buffer that decouples the power consumption dependency with the closed loop gain. The prototype was designed in 40 nm CMOS technology achieving 64.9 dB peak SNDR. The operating frequency was 3.2 GHz, the total power consumption was 22 mW and FoM of 106 fJ/conversion-step. In a third project, the same approach of decoupling the power consumption requirements from the closed loop gain is applied to a pipelined ADC. The traditional capacitive multiplying DAC used in the residual amplifier is substituted by a current mode DAC and a transimpedance amplifier. The prototype was implemented in 40 nm CMOS technology achieving 58 dB peak SNDR and 76 dB SFDR with 200 MHz sampling frequency. The ADC consumes 8.4 mW with a FoM of 64 fJ/Conversion-step

High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion

The purpose of this thesis is the proposal and implementation of data conversion open-loop architectures based on voltage-controlled oscillators (VCOs) built with ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to the newest complementary metal-oxide-semiconductor (CMOS) nodes. The scaling of the design technologies into the nanometer range imposes the reduction of the supply voltage towards small and power-efficient architectures, leading to lower voltage overhead of the transistors. Additionally, phenomena like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between devices and PVT variations) make the design of classic structures for ADCs more challenging. In recent years, time-encoded A/D conversion has gained relevant popularity due to the possibility of being implemented with mostly digital structures. Within this trend, VCOs designed with ring oscillator based topologies have emerged as promising candidates for the conception of new digitization techniques. RO-based data converters show excellent scalability and sensitivity, apart from some other desirable properties, such as inherent quantization noise shaping and implicit anti-aliasing filtering. However, their nonlinearity and the limited time delay achievable in a simple NOT gate drastically limits the resolution of the converter, especially if we focus on wide-band A/D conversion. This thesis proposes new ways to alleviate these issues. Firstly, circuit-based techniques to compensate for the nonlinearity of the ring oscillator are proposed and compared to equivalent state-of-the-art solutions. The proposals are designed and simulated in a 65-nm CMOS node for open-loop RO-based ADC architectures. One of the techniques is also validated experimentally through a prototype. Secondly, new ways to artificially increase the effective oscillation frequency are introduced and validated by simulations. Finally, new approaches to shape the quantization noise and filter the output spectrum of a RO-based ADC are proposed theoretically. In particular, a quadrature RO-based band-pass ADC and a power-efficient Nyquist A/D converter are proposed and validated by simulations. All the techniques proposed in this work are especially devoted for highbandwidth applications, such as Internet-of-Things (IoT) nodes or maximally digital radio receivers. Nevertheless, their field of application is not restricted to them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas de conversión de datos basadas en osciladores en anillos, compatibles con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación más modernos donde las estructuras digitales se ven favorecidas. La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción de la tensión de alimentación para el desarrollo de arquitecturas pequeñas y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión para saturar transistores, lo que añadido a una ganancia cada vez menor de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones de proceso, tensión y temperatura han llevado a que sea cada vez más complejo el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión A/D basada en codificación temporal ha ganado gran popularidad dado que permite la implementación de estructuras mayoritariamente digitales. Como parte de esta evolución, los osciladores controlados por tensión diseñados con topologías de oscilador en anillo han surgido como un candidato prometedor para la concepción de nuevas técnicas de digitalización. Los convertidores de datos basados en osciladores en anillo son extremadamente sensibles (variación de frecuencia con respecto a la señal de entrada) así como escalables, además de otras propiedades muy atractivas, como el conformado espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta NOT restringen la resolución del conversor, especialmente para conversión A/D en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas técnicas para aliviar este tipo de problemas. En primer lugar, se proponen técnicas basadas en circuito para compensar el efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas presentadas es también validada experimentalmente a través de un prototipo. En segundo lugar, se introducen y validan por simulación varias formas de incrementar artificialmente la frecuencia de oscilación efectiva. Para finalizar, se proponen teóricamente dos enfoques para configurar nuevas formas de conformación del ruido de cuantificación y filtrado del espectro de salida de los datos digitales. En particular, son propuestos y validados por simulación un ADC pasobanda en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente para aplicaciones de alto ancho de banda, tales como módulos para el Internet de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar de ello, son extrapolables también a otros campos como el de la instrumentación biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí

Analysis of Current Conveyor based Switched Capacitor Circuits for Application in ∆Σ Modulators

The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals. The Delta Sigma (∆Σ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications. However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers. In this thesis we present an alternative approach to design of ∆Σ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area. The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) ∆Σ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity

The Music Sound

A guide for music: compositions, events, forms, genres, groups, history, industry, instruments, language, live music, musicians, songs, musicology, techniques, terminology , theory, music video. Music is a human activity which involves structured and audible sounds, which is used for artistic or aesthetic, entertainment, or ceremonial purposes. The traditional or classical European aspects of music often listed are those elements given primacy in European-influenced classical music: melody, harmony, rhythm, tone color/timbre, and form. A more comprehensive list is given by stating the aspects of sound: pitch, timbre, loudness, and duration. Common terms used to discuss particular pieces include melody, which is a succession of notes heard as some sort of unit; chord, which is a simultaneity of notes heard as some sort of unit; chord progression, which is a succession of chords (simultaneity succession); harmony, which is the relationship between two or more pitches; counterpoint, which is the simultaneity and organization of different melodies; and rhythm, which is the organization of the durational aspects of music