Solving mazes with memristors: a massively-parallel approach

Solving mazes is not just a fun pastime. Mazes are prototype models in graph theory, topology, robotics, traffic optimization, psychology, and in many other areas of science and technology. However, when maze complexity increases their solution becomes cumbersome and very time consuming. Here, we show that a network of memristors - resistors with memory - can solve such a non-trivial problem quite easily. In particular, maze solving by the network of memristors occurs in a massively parallel fashion since all memristors in the network participate simultaneously in the calculation. The result of the calculation is then recorded into the memristors’ states, and can be used and/or recovered at a later time. Furthermore, the network of memristors finds all possible solutions in multiple-solution mazes, and sorts out the solution paths according to their length. Our results demonstrate not only the first application of memristive networks to the field of massively-parallel computing, but also a novel algorithm to solve mazes which could find applications in different research fields

Analog-to-Digital and Digital-to-Analog Conversion with Memristive Devices

We suggest a novel methodology to obtain a digital representation of analog signals and to perform its back-conversion using memristive devices. In the proposed converters, the same memristive systems are used for two purposes: as elements performing conversion and elements storing the code. This approach to conversion is particularly relevant for interfacing analog signals with memristive digital logic/computing circuits

Ge2Sb2Te5 layer used as solid electrolyte in conductive-bridge memory devices fabricated on flexible substrate

7 pagesInternational audienceThis paper shows that the well-know chalcogenide Ge2Sb2Te5 (GST) in its amorphous state may be advantageously used as solid electrolyte material to fabricate Conductive-Bridge Random Access Memory (CBRAM) devices. GST layer was sputtered on preliminary inkjet-printed silver lines acting as active electrode on either silicon or plastic substrates. Whatever the substrate, the resistance switching is unambiguously attested at a nanoscale by means of conductive-atomic force microscopy (C-AFM) using a Pt-Ir coated tip on the GST surface acting as a passive electrode. The resistance change is correlated to the appearance or disappearance of concomitant hillocks and current spots at the surface of the GST layer. This feature is attributed to the formation/dissolution of a silver-rich protrusion beneath the AFM tip during set/reset operation. Beside, this paper constitutes a step toward the elaboration of crossbar memory arrays on flexible substrates since CBRAM operations were demonstrated on W/GST/Ag crossbar memory cells obtained from an heterogeneous fabrication process combining physical deposition and inkjet-printing

High speed chalcogenide glass electrochemical metallization cells with various active metals

We fabricated electrochemical metallization (ECM) cells using a GaLaSO solid electrolyte, a InSnO inactive electrode and active electrodes consisting of various metals (Cu, Ag, Fe, Cu, Mo, Al). Devices with Ag and Cu active metals showed consistent and repeatable resistive switching behaviour, and had a retention of 3 and >43 days, respectively; both had switching speeds of < 5 ns. Devices with Cr and Fe active metals displayed incomplete or intermittent resistive switching, and devices with Mo and Al active electrodes displayed no resistive switching ability. Deeper penetration of the active metal into the GaLaSO layer resulted in greater resistive switching ability of the cell. The off-state resistivity was greater for more reactive active metals which may be due to a thicker intermediate layer

Conductive bridging RAM devices inspired on solid-state biopolymer electrolytes

This work reports the design, fabrication and characterization of metal-insulator-metal (MIM) structures acting as conductive bridging random access memory (CBRAM) devices using biopolymer insulator. Chitosan and hydroxypropyl cellulose (HPC) were deposited by spin coating in between evaporated Pt and Ag electrodes. CBRAM devices fabricated using chitosan as the insulating layer demonstrated retention times of up to 105 s with an on/off ratio of 102 as well as enduring several program/erase cycles. Devices fabricated with HPC showed retention times of up to 104 s with an on/off ratio of approximately 106, and also showed stable device operation over several cycles. Furthermore, the functionalization of chitosan with silver nanoparticles and its integration in the MIM structures were investigated, as well as the substitution of the e-beam evaporated Ag electrode by a screen printed Ag electrode

Nouvelles Architectures Hybrides (Logique / Mémoires Non-Volatiles et technologies associées.)

Les nouvelles approches de technologies mémoires permettront une intégration dite back-end, où les cellules élémentaires de stockage seront fabriquées lors des dernières étapes de réalisation à grande échelle du circuit. Ces approches innovantes sont souvent basées sur l'utilisation de matériaux actifs présentant deux états de résistance distincts. Le passage d'un état à l'autre est contrôlé en courant ou en tension donnant lieu à une caractéristique I-V hystérétique. Nos mémoires résistives sont composées d'argent en métal électrochimiquement actif et de sulfure amorphe agissant comme électrolyte. Leur fonctionnement repose sur la formation réversible et la dissolution d'un filament conducteur. Le potentiel d'application de ces nouveaux dispositifs n'est pas limité aux mémoires ultra-haute densité mais aussi aux circuits embarqués. En empilant ces mémoires dans la troisième dimension au niveau des interconnections des circuits logiques CMOS, de nouvelles architectures hybrides et innovantes deviennent possibles. Il serait alors envisageable d'exploiter un fonctionnement à basse énergie, à haute vitesse d'écriture/lecture et de haute performance telles que l'endurance et la rétention. Dans cette thèse, en se concentrant sur les aspects de la technologie de mémoire en vue de développer de nouvelles architectures, l'introduction d'une fonctionnalité non-volatile au niveau logique est démontrée par trois circuits hybrides: commutateurs de routage non volatiles dans un Field Programmable Gate Arrays, un 6T-SRAM non volatile, et les neurones stochastiques pour un réseau neuronal. Pour améliorer les solutions existantes, les limitations de la performances des dispositifs mémoires sont identifiés et résolus avec des nouveaux empilements ou en fournissant des défauts de circuits tolérants.Novel approaches in the field of memory technology should enable backend integration, where individual storage nodes will be fabricated during the last fabrication steps of the VLSI circuit. In this case, memory operation is often based upon the use of active materials with resistive switching properties. A topology of resistive memory consists of silver as electrochemically active metal and amorphous sulfide acting as electrolyte and relies on the reversible formation and dissolution of a conductive filament. The application potential of these new memories is not limited to stand-alone (ultra-high density), but is also suitable for embedded applications. By stacking these memories in the third dimension at the interconnection level of CMOS logic, new ultra-scalable hybrid architectures becomes possible which exploit low energy operation, fast write/read access and high performance with respect to endurance and retention. In this thesis, focusing on memory technology aspects in view of developing new architectures, the introduction of non-volatile functionality at the logic level is demonstrated through three hybrid (CMOS logic ReRAM devices) circuits: nonvolatile routing switches in a Field Programmable Gate Array, nonvolatile 6T-SRAMs, and stochastic neurons of an hardware neural network. To be competitive or even improve existing solutions, limitations on the memory devices performances are identified and solved by stack engineering of CBRAM devices or providing faults tolerant circuits.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Evaluation des performances des mémoires CBRAM (Conductive bridge memory) afin d’optimiser les empilements technologiques et les solutions d’intégration

The constant evolution of the data storage needs over the last decades have led the technological landscape to completely change and reinvent itself. From the early stage of magnetic storage to the most recent solid state devices, the bit density keeps increasing toward what seems from a consumer point of view infinite storage capacity and performances. However, behind each storage technology transition stand density and performances limitations that required strong research work to overcome. This manuscript revolves around one of the promising emerging technology aiming to revolutionize data storage landscape: the Conductive Bridge Random Access Memory (CBRAM). This technology based on the reversible formation and dissolution of a conductive path in a solid electrolyte matrix offers great advantages in term of power consumption, performances, density and the possibility to be integrated in the back end of line. However, for this technology to be competitive some roadblocks still have to be overcome especially regarding the technology variability, reliability and thermal stability. This manuscript proposes a comprehensive understanding of the CBRAM operations based on experimental results and a specially developed Kinetic Monte Carlo model. This understanding creates bridges between the physical properties of the materials involved in the devices and the devices performances (Forming, SET and RESET time and voltage, retention, endurance, variability). A strong emphasis is placed on the current limitations of the technology previously stated and how to overcome these limitations. Improvement of the thermal stability and device reliability are demonstrated with optimized operating conditions and proper devices engineering.Ces dernières décennies, la constante évolution des besoins de stockage de données a mené à un bouleversement du paysage technologique qui s’est complètement métamorphosé et réinventé. Depuis les débuts du stockage magnétique jusqu’aux plus récents dispositifs fondés sur l’électronique dit d’état solide, la densité de bits stockés continue d’augmenter vers ce qui semble du point de vue du consommateur comme des capacités de stockage et des performances infinies. Cependant, derrière chaque transition et évolution des technologies de stockage se cachent des limitations en termes de densité et performances qui nécessitent de lourds travaux de recherche afin d’être surmontées et repoussées. Ce manuscrit s’articule autour d’une technologie émergeante prometteuse ayant pour vocation de révolutionner le paysage du stockage de données : la mémoire à pont conducteur ou Conductive Bridge Random Access Memory (CBRAM). Cette technologie est fondée sur la formation et dissolution réversible d’un chemin électriquement conducteur dans un électrolyte solide. Elle offre de nombreux avantages face aux technologies actuelles tels qu’une faible consommation électrique, de très bonnes performances d’écriture et de lecture et la capacité d’être intégré aux seins des interconnexions métalliques d’une puce afin d’augmenter la densité de stockage. Malgré tout, pour que cette technologie soit compétitive certaines limitations ont besoin d’être surmontées et particulièrement sa variabilité et sa stabilité thermique qui posent encore problème. Ce manuscrit propose une compréhension physique globale du fonctionnement de la technologie CBRAM fondée sur une étude expérimentale approfondie couplée à un modèle Monte Carlo cinétique spécialement développé. Cette compréhension fait le lien entre les propriétés physiques des matériaux composant la mémoire CBRAM et ses performances (Tension et temps d’écriture et d’effacement, rétention de donnée, endurance et variabilité). Un fort accent est mis la compréhension des limites actuelle de la technologie et comment les repousser. Grâce à une optimisation des conditions d’opérations ainsi qu’à un travail d’ingénierie des dispositifs mémoire, il est démontré dans ce manuscrit une forte amélioration de la stabilité thermique ainsi que de la variabilité des états écrits et effacés