Structured, technology independent VLSI design

Journal ArticleRapid advancement in new semiconductor technologies has created a need for the design of existing integrated circuits using these new technologies. These new technologies are required to provide improved performance, smaller feature sizes and lower costs. The conversion of an integrated circuit from an existing technology to a new technology, however, is very difficulty with existing CAD tools. In this research, we have concentrated on developing a structured, technology independent VLSI design methodology, with the goal of theoretically quantifying technology independence and systematically performing technology transformation. We have identified the nature of the problems, using techniques developed during our past research, within the context of particular semiconductor technologies such as CMOS and GaAs technologies

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2

Miniaturizing High Throughput Droplet Assays For Ultrasensitive Molecular Detection On A Portable Platform

Digital droplet assays – in which biological samples are compartmentalized into millions of femtoliter-volume droplets and interrogated individually – have generated enormous enthusiasm for their ability to detect biomarkers with single-molecule sensitivity. These assays have untapped potential for point-of-care diagnostics but are mainly confined to laboratory settings due to the instrumentation necessary to serially generate, control, and measure millions of compartments. To address this challenge, we developed an optofluidic platform that miniaturizes digital assays into a mobile format by parallelizing their operation. This technology has three key innovations: 1. the integration and parallel operation of hundred droplet generators onto a single chip that operates \u3e100x faster than a single droplet generator. 2. the fluorescence detection of droplets at \u3e100x faster than conventional in-flow detection using time-domain encoded mobile-phone imaging, and 3. the integration of on-chip delay lines and sample processing to allow serum-to-answer device operation. By using this time-domain modulation with cloud computing, we overcome the low framerate of digital imaging, and achieve throughputs of one million droplets per second. To demonstrate the power of this approach, we performed a duplex digital enzyme-linked immunosorbent assay (ELISA) in serum to show a 1000x improvement over standard ELISA and matching that of the existing laboratory-based gold standard digital ELISA system. This work has broad potential for ultrasensitive, highly multiplexed detection, in a mobile format. Building on our initial demonstration, we explored the following: (i) we demonstrated that the platform can be extended to \u3e100x multiplexing by using time-domain encoded light sources to detect color-coded beads that each correspond to a unique assay, (ii) we demonstrated that the platform can be extended to the detection of nucleic acid by implementing polymerase chain reaction, and (iii) we demonstrated that sensitivity can be improved with a nanoparticle-enhanced ELISA. Clinical applications can be expanded to measure numerous biomarkers simultaneously such as surface markers, proteins, and nucleic acids. Ultimately, by building a robust device, suitable for low-cost implementation with ultrasensitive capabilities, this platform can be used as a tool to quantify numerous medical conditions and help physicians choose optimal treatment strategies to enable personalized medicine in a cost-effective manner