Barrel Shifter Physical Unclonable Function Based Encryption

Physical Unclonable Functions (PUFs) are circuits designed to extract physical randomness from the underlying circuit. This randomness depends on the manufacturing process. It differs for each device enabling chip-level authentication and key generation applications. We present a protocol utilizing a PUF for secure data transmission. Parties each have a PUF used for encryption and decryption; this is facilitated by constraining the PUF to be commutative. This framework is evaluated with a primitive permutation network - a barrel shifter. Physical randomness is derived from the delay of different shift paths. Barrel shifter (BS) PUF captures the delay of different shift paths. This delay is entangled with message bits before they are sent across an insecure channel. BS-PUF is implemented using transmission gates; their characteristics ensure same-chip reproducibility, a necessary property of PUFs. Post-layout simulations of a common centroid layout 8-level barrel shifter in 0.13 {\mu}m technology assess uniqueness, stability and randomness properties. BS-PUFs pass all selected NIST statistical randomness tests. Stability similar to Ring Oscillator (RO) PUFs under environment variation is shown. Logistic regression of 100,000 plaintext-ciphertext pairs (PCPs) failed to successfully model BS- PUF behavior

Reliability Enhancement Of Ring Oscillator Based Physically Unclonable Functions

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2012Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2012Bu çalışmada, halka osilatör tabanlı fiziksel klonlanamayan fonksiyon devrelerinin, çeşitli çevresel etkiler karşısında güvenilirliklerin artırılması amaçlanmıştır. Öncelikle, osilatör çiftlerinin ürettiği frekans farklılıklarını ve dinamik etkileri gözlemleyip modelleyebilmek için çeşitli sahada programlanabilir kapı dizilerinin (FPGA) farklı bölgelerinde osilatör çiftleri gerçeklenmiş ve frekans farklılıkları ölçülmüştür. Bu ölçümler sonucunda halka osilatör çiftlerinine ilişkin statik ve dinamik dağılımlar elde edilmiştir. Güvenilirliği artırmak amacıyla halka osilatörleri etiketleyen bir yöntem önerilmiştir. Bu çalışmada ayrıca, bir osilatör çiftinden birden fazla bit elde etme işlemi de incelenmiş ve dinamik etkilere karşı test edilmiştir. Etiketleme yönteminin etkinliğini ve bir osilatör çiftinden birden fazla bit elde etme işlemini gerçek devre üzerinde incelemek amacıyla, fiziksel klonlanamayan fonksiyon devresi FPGA üzerinde gerçeklenmiştir. Sıcaklık odası ile ortamın sıcaklığı 10 – 65 °C arasında değiştirilmiştir. Sonuç olarak, ortam sıcaklığının artmasıyla birlikte güvenilmez bit sayısının arttığı gözlenmiştir. Etiketleme yöntemi kullanıldığında güvenilmez bite rastlanmamıştır. Bir halka osilatör çiftinden birden fazla bit (iki ve üç bit bilgi) elde edilmesi de test edilmiştir. Elde edilen iki ve üç bitlik verilerin küçük bir farklılıkla birlikte eşit dağılımlı olduğu gözlenmiştir. Bir osilatör çiftinden elde edilen bit sayısı arttıkça, güvenilir olmayan bitlerin sayısı da artmıştır. Fakat bir osilatörden iki ve üç bit elde etmede tüm hataların komşu bölgede olduğu gözlenmiştir.In this thesis, it is aimed to enhance the reliability of ring oscillator based Physically Unclonable Functions (PUFs) under different environmental variations. In order to observe and model the frequency difference of ring oscillator pairs and dynamic effects, ring oscillators are realized and measured at different locations of different Field Programmable Gate Arrays (FPGAs). After the measurements, static and dynamic distributions of ring oscillator pairs are obtained. In order to increase the reliability, a new technique that is labeling ring oscillators, is proposed. Also, in this study, the process of obtaining multiple bits from a ring oscillator pair is observed and tested with respect to dynamic effects. In order to analyze the enhancement of labeling technique and multiple bit extraction at the circuit, the PUF circuit is implemented on an FPGA. The ambient temperature is changed between 10 – 65 °C with a temperature chamber. As a result, it is observed that with increasing ambient temperature, the number of unreliable bits are increased. When labeling technique is used, no unreliable bits are observed. Multiple bits extraction (two and three bits extraction) is also tested. It is observed that the distribution of two and three bit wide data are almost equally distributed. The number of unreliable bits are increased with the extracted bit numbers. However, it is seen that all erronous bits are caused by jumping to adjacent region.Yüksek LisansM.Sc

Delay-based Physical Unclonable Function Implementation

As we venture further into the 21st century, it becomes much clearer that hardware security is at the forefront of many challenges that we face today in ensuring that data is protected. “Keys” (a sequence of bits) can be used to unlock pieces of data and is a concept that is pervasive throughout cryptography, but storage in memory makes this sole method nonviable. To make the approach more practical, one can dynamically generate a key through a Physical Unclonable Function (PUF). PUFs are circuit primitives that use intrinsic variations of microchips created during the manufacturing process to generate a unique “fingerprint” for each chip. We simulated several different PUF designs on a Field Programmable Gate Array (FPGA) board to determine how changes to a starting design can affect the reliability, randomness, and uniqueness of these IDs. We propose two schemes, a parallel and a serial scheme for a ring oscillator (RO) based PUF. The parallel scheme is a useful benchmark for other designs, and the serial scheme uses much less hardware than other RO PUF designs. The serial scheme is not as random, reliable, or unique as the parallel scheme, but it creates input-output pairs with much less area

An Improved Public Unclonable Function Design for Xilinx FPGAs for Hardware Security Applications

In the modern era we are moving towards completely connecting many useful electronic devices to each other through internet. There is a great need for secure electronic devices and systems. A lot of money is being invested in protecting the electronic devices and systems from hacking and other forms of malicious attacks. Physical Unclonable Function (PUF) is a low-cost hardware scheme that provides affordable security for electronic devices and systems. This thesis proposes an improved PUF design for Xilinx FPGAs and evaluates and compares its performance and reliability compared to existing PUF designs. Furthermore, the utility of the proposed PUF was demonstrated by using it for hardware Intellectual Property (IP) core licensing and authentication. Hardware Trojan can be used to provide evaluation copy of IP cores for a limited time. After that it disables the functionality of the IP core. A finite state machine (FSM) based hardware trojan was integrated with a binary divider IP core and evaluated for licensing and authentication applications. The proposed PUF was used in the design of hardware trojan. Obfuscation metric measures the effectiveness of hardware trojan. A moderately good obfuscation level was achieved for our hardware trojan

Hybrid PUF Design using Bistable Ring PUF and Chaotic Network

Physical Unclonable Function(PUF) is lightweight hardware that provides affordable security for electronic devices and systems which can eliminate the use of the conventional cryptographic system which uses large area and storage. Among the several models, Bi-stable Ring PUF(BR-PUF) is considered as a secure and efficient PUF model since it has no mathematical model still found. In this thesis, we proposed a modified design called a hybrid model of BR-PUF and a Chaotic network to improve the BR-PUF resilience against machine learning attacks. We experimented with the current modification XOR technique to analyze the uniqueness, reliability and resource consumption. The proposed PUF was implemented on Xilinx Artix 7 FPGA and the PUF metrics were captured and compared with the results of XOR-ed based PUF integration techniques. The lightweight PUF model was achieved with 16% resource reduction when compared to XOR-ed BR PUF with no compromise in PUF quality

Securing IEEE P1687 On-chip Instrumentation Access Using PUF

As the complexity of VLSI designs grows, the amount of embedded instrumentation in system-on-a-chip designs increases at an exponential rate. Such structures serve various purposes throughout the life-cycle of VLSI circuits, e.g. in post-silicon validation and debug, production test and diagnosis, as well as during in-field test and maintenance. Reliable access mechanisms for embedded instruments are therefore key to rapid chip development and secure system maintenance. Reconfigurable scan networks defined by IEEE Std. P1687 emerge as a scalable and cost-effective access medium for on-chip instrumentation. The accessibility offered by reconfigurable scan networks contradicts security and safety requirements for embedded instrumentation. Embedded instrumentation is an integral system component that remains functional throughout the lifetime of a chip. To prevent harmful activities, such as tampering with safety-critical systems, and reduce the risk of intellectual property infringement, the access to embedded instrumentation requires protection. This thesis provides a novel, Physical Unclonable Function (PUF) based secure access method for on-chip instruments which enhances the security of IJTAG network at low hardware cost and with less routing congestion

Physical Unclonable Function Techniques Applied for Digital Hardware Protection

Privacy is an important property that is growing harder to keep as people develop new ways to steal information from users on their computers. Software alone cannot ensure privacy since an infected system is untrustworthy. This paper presents several challenges malware brings that can be solved by using an external processor. Techniques such as keystroke encryption and message authentication can be used to protect users from having their passwords and other private data stolen. To take advantage of the external hardware, a physical unclonable function can be used to generate private keys without the need for storing them in memory. In this report, a design of a physical unclonable function is detailed and designed for use on an FPGA. Two different types of hardware design software are briefly discussed for the purpose of choosing the superior tool for creating a PUF on an FPGA