D/A Resolution Impact on a Poly-phase Multipath Transmitter

In recent publications the Poly-phase multipath technique has been shown to produce a clean output spectrum for a power upconverter (PU) architecture. The technique utilizes frequency independent phase shifts before and after a nonlinear element to cancel out the harmonics and sidebands due to the nonlinearity. A major advantage of this technique is that it circumvents the need to use dedicated RF filters which makes it a potential candidate for cognitive radio transmitters. This paper addresses the requirements on the digital and mixed signal part of such a transmitter. An architecture is proposed based on complex multiplication which can be used to generate the digital multiphase signals required by the multipath technique. Due to equal phase difference of all the paths the same digital hardware could be utilized for carrying out all the phase shifts. When the digital signals pass through a D/A converter which doesn’t have a reconstruction filter, the output in this case would be amplitude discrete like that of a zero order hold. The spectrum of this amplitude discrete signal would have distortion components in it. This can be termed as quantization distortion but now in the context of limited D/A resolution. The multipath technique’s effect on harmonic cancellation, in the presence of such a quantization distortion is explored in this paper. It is shown through simulation that when using ideal phase shifts the multipath technique is able to cancel most of the harmonics produced by an amplitude discrete representation of pure sinusoids. When (upconversion) mixers are used for the second set of phase shifts then with multipath the highest quantization spurs go down with roughly 8db/bit for a single tone and around 10db/bit for two tone inputs

A Polyphase Multipath Technique for Software-Defined Radio Transmitters

Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a software-defined radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 Vpp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixer

Linearity and Noise Improvement Techniques Employing Low Power in Analog and RF Circuits and Systems

The implementation of highly integrated multi-bands and multi-standards reconfigurable radio transceivers is one of the great challenges in the area of integrated circuit technology today. In addition the rapid market growth and high quality demands that require cheaper and smaller solutions, the technical requirements for the transceiver function of a typical wireless device are considerably multi-dimensional. The major key performance metrics facing RFIC designers are power dissipation, speed, noise, linearity, gain, and efficiency. Beside the difficulty of the circuit design due to the trade-offs and correlations that exist between these parameters, the situation becomes more and more challenging when dealing with multi-standard radio systems on a single chip and applications with different requirements on the radio software and hardware aiming at highly flexible dynamic spectrum access. In this dissertation, different solutions are proposed to improve the linearity, reduce the noise and power consumption in analog and RF circuits and systems. A system level design digital approach is proposed to compensate the harmonic distortion components produced by transmitter circuits’ nonlinearities. The approach relies on polyphase multipath scheme uses digital baseband phase rotation pre-distortion aiming at increasing harmonic cancellation and power consumption reduction over other reported techniques. New low power design techniques to enhance the noise and linearity of the receiver front-end LNA are also presented. The two proposed LNAs are fully differential and have a common-gate capacitive cross-coupled topology. The proposed LNAs avoids the use of bulky inductors that leads to area and cost saving. Prototypes are implemented in IBM 90 nm CMOS technology for the two LNAs. The first LNA covers the frequency range of 100 MHz to 1.77 GHz consuming 2.8 mW from a 2 V supply. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB while the input return loss is greater than 10 dB across the entire band. The second LNA covers the frequency range of 100 MHz to 1.6 GHz. A 6 dBm third-order input intercept point, IIP3, is measured at the maximum gain frequency. The core consumes low power of 1.55 mW using a 1.8 V supply. The measured voltage gain is 15.5 dB with a 3-dB bandwidth of 1.6 GHz. The LNA has a minimum NF of 3 dB across the whole band while achieving an input return loss greater than 12 dB. Finally, A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth (GBW). The OTA is fabricated on the AMI 0.5 um CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB till 10 KHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers a very low current consumption of 25 uA from a 3.3 V supply

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Low Power High Efficiency Integrated Class-D Amplifier Circuits for Mobile Devices

The consumer’s demand for state-of-the-art multimedia devices such as smart phones and tablet computers has forced manufacturers to provide more system features to compete for a larger portion of the market share. The added features increase the power consumption and heat dissipation of integrated circuits, depleting the battery charge faster. Therefore, low-power high-efficiency circuits, such as the class-D audio amplifier, are needed to reduce heat dissipation and extend battery life in mobile devices. This dissertation focuses on new design techniques to create high performance class-D audio amplifiers that have low power consumption and occupy less space. The first part of this dissertation introduces the research motivation and fundamentals of audio amplification. The loudspeaker’s operation and main audio performance metrics are examined to explain the limitations in the amplification process. Moreover, the operating principle and design procedure of the main class-D amplifier architectures are reviewed to provide the performance tradeoffs involved. The second part of this dissertation presents two new circuit designs to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers. The first work proposes a feed-forward power-supply noise cancellation technique for single-ended class-D amplifier architectures to improve the power-supply rejection ratio across the entire audio frequency range. The design methodology, implementation, and tradeoffs of the proposed technique are clearly delineated to demonstrate its simplicity and effectiveness. The second work introduces a new class-D output stage design for piezoelectric speakers. The proposed design uses stacked-cascode thick-oxide CMOS transistors at the output stage that makes possible to handle high voltages in a low voltage standard CMOS technology. The design tradeoffs in efficiency, linearity, and electromagnetic interference are discussed. Finally, the open problems in audio amplification for mobile devices are discussed to delineate the possible future work to improve the performance of class-D amplifiers. For all the presented works, proof-of-concept prototypes are fabricated, and the measured results are used to verify the correct operation of the proposed solutions

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

Surpassing Fundamental Limits through Time Varying Electromagnetics

Surpassing the fundamental limits that govern all electromagnetic structures, such as reciprocity and the delay-bandwidth-size limit, will have a transformative impact on all applications based on electromagnetic circuits and systems. For instance, violating principles of reciprocity enables non-reciprocal components such as isolators and circulators, which find application in full-duplex wireless radios, radar, biomedical imaging, and quantum computing systems. Overcoming the delay-bandwidth-size limit enables ultra-broadband yet extremely-compact devices whose size is not fundamentally related to the wavelength at the operating frequency. The focus of this dissertation is on using time-variance as a new toolbox to overcome these fundamental limits and re-imagine circuit and system design. Traditional non-reciprocal components are realized using ferrite materials that loose their reciprocity under the application of external magnetic bias. However, the sheer volume, cost and weight of these magnet based non-reciprocal components coupled with their inability to be fabricated in conventional semiconductor processes, have limited their application to bulky and large-scale systems. Other approaches such as active-biased and non-linearity based non-reciprocity are compatible with semiconductor processes, however, they suffer from other poor linearity and noise performance. In this dissertation, using passive transistor switch as the modulating element, we have proposed the concept of spatio-temporal conductivity modulation and have demonstrated a gamut of non-reciprocal devices ranging from gyrators to isolators and circulators. Through novel circuit topologies, for the first time, we have demonstrated on-chip circulators with multi-watt input power handling, operation at high millimeter-wave frequencies, and tailor made circulators for emerging technologies such as simultaneous-transmit-and-receive MRI and quantum computing. Delay-bandwidth-size trade-off is another fundamental electromagnetic limit, that constrains the delay imparted by a medium or a device within a fixed footprint to be inversely proportional to the signal bandwidth. It is this limit that governs the size of any microwave passive devices to be inversely proportional to its operating frequency. As a part of this dissertation, through intelligent clocking of switched capacitor networks we overcame the delay-bandwidth-size limit, thus resulting in infinitesimal, yet broadband microwave devices. Here we proposed a new paradigm in wave propagation where the properties such as the propagation delay and characteristic impedance does not depend on the constituent elements/materials of the medium, but rather heavily rely on the user-defined modulation scheme, thereby opening huge opportunities for realizing highly-reconfigurable passives. Leveraging these concepts, we demonstrated wide range of reciprocal an non-reciprocal devices including ultra-compact delay elements, highly-reconfigurable microwave passives, ultra-wideband circulators with infinitesimal form-factors and dispersion-free chip scale floquet topological insulators. Application of these devices have also been evaluated in real-world systems through our demonstrations of wideband, full-duplex receivers leveraging switched capacitors based true-time-delay interference cancelers and floquet topological insulator based antenna interfaces for full-duplex phased-arrays and ultra-wideband beamformers. Furthermore, to cater the growing RF and microwave needs of future, large-scale quantum computing systems, we demonstrated a low-cryogenic, wideband circulator based on time modulation of superconducting devices. This superconducting circulator is expected to operate alongside the superconducting qubits, inside a dilution refrigerator at 10mK-100mK, thus enabling a tightly integrated quantum system. We also presented the design and implementation of a cryogenic-CMOS clock driver chip that will generate the clocks required by the superconducting circulator. Finally, we also demonstrated the design and implementation of a low-noise, low power consumption, 6GHz - 8GHz cryogenic downconversion receiver at 4K for cryogenic qubit readout

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs