Electron effective mobility in strained Si/Si1-xGex MOS devices using Monte Carlo simulation

Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si1-xGex MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves mueff as a function of the effective vertical field Eeff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si0.70Ge0.30, in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only. The role of the different scattering mechanisms involved in the strained Si/ Si1-xGex MOS structures is explained. In addition, comparison with experimental results is discussed in terms of SiO2/ Si interface roughness, as well as surface roughness of the SiGe substrate on which strained Si is grown.Comment: 25 pages, 8 figures, 1 table, revised version, discussions and references adde

Monte Carlo simulation of silicon-germanium transistors

Self-consistent Monte Carlo simulation studies of n-channel Si/SiGe modulation doped field effect transistors (MODFETs) and silicon-on-insulator lateral bipolar junction transistors (SOI- LBJTs) are reported in this thesis. As a preliminary to the device studies Monte Carlo simulations of electron transport in bulk Si strained as if grown on Si(_0.77)Ge(_0.23) and Si(_0.55)Ge(_0.45) substrates have been carried out at 300 K, for field strengths varied from 10(^4) to 2 x 10(^7) Vm(^-1). The calculations indicate an enhancement of the average electron drift velocity when Si is tensilely strained in the growth plane. The enhancement of electron velocity is more marked at low and intermediate electric fields, while at very high fields the velocity saturates at about the same value as unstrained Si. In addition the ensemble Monte Carlo method has been used to study the transient response to a stepped electric field of electrons in strained and unstrained Si. The calculations suggest that significant velocity overshoots occurs in strained material. Simulations of n-channel Si/Si(_1=z)Ge(_z) MODFETs with Ge fractions of 0.23, 0.25, and 0.45 have been performed. Five depletion mode devices with x = 0.23 and 0.25 were studied. The simulations provide information on the microscopic details of carrier behaviour, including carrier velocity, kinetic energy and carrier density, as a function of position in the device. Detailed time-dependent voltage signal analysis has been carried out to test device response and derive the frequency bandwidth. The simulations predict a current gain cut-off frequency of 60 ± 10 GHz for a device with a gate length of 0.07 /nm and a channel length of 0.25 um. Similar studies of depletion and enhancement mode n-channel Si/Sio.55Geo.45 MODFETs with a gate length of 0.18 /im have been carried out. Cut-off frequencies of 60 ±10 GHz and 90± 10 GHz are predicted for the depletion and enhancement mode devices respectively. A Monte Carlo model has also been devised and used to simulate steady state and transient electron and hole transport in SOI-LBJTs. Four devices have been studied and the effects of junction depth and silicon layer thickness have been investigated. The advantage of the silicon-on-insulator technology SOI device is apparent in terms of higher collector current, current gain, and cut-off frequency obtained in comparison with an all-silicon structure. The simulations suggest that the common-emitter current gain of the most promising SOI-LBJT structure considered could have a cut-off frequency approaching 35 ± 5 GHz

Simulation and Optimisation of SiGe MOSFETs

This research project is concerned with the development of methodology for simulating advanced SiGe MOSFETs using commercial simulators, the calibration of simulators against higher level Monte Carlo simulation results and real device measurements, and the application of simulation tools in the design of next generation p- channel devices. The methodology for the modelling and simulation of SiGe MOSFET devices is outlined. There are many simulation approaches widely used to simulate SiGe devices, such as Monte Carlo, hydrodynamic, energy transport, and drift diffusion. Different numerical techniques including finite difference, finite box and finite element methods, may be used in the simulators. The Si0.8Ge0.2 p-MOSFETs fabricated especially for high-field transport studies and the Si0.64Ge0.36 p-channel MOSFETs fabricated at Warwick and Southampton Universities with a CMOS compatible process in varying gate lengths were calibrated and investigated. Enhanced low field mobility in SiGe layers compared to Si control devices was observed. The results indicated that the potential of velocity overshoot effects for SiGe p-MOSFETs was considerably higher than Si counterparts, promising higher performance in the former at equal gate lengths at ultra-small devices. The effects of punchthrough stopper, undoped buffers and delta doping for SiGe p-MOSFETs were analysed systematically. It was found that the threshold voltage roll off might be reduced considerably by using an appropriate punchthrough stopper. In order to adjust the threshold voltage for digital CMOS applications, p-type delta doping was required for n+-polysilicon gate p-MOSFET. The use of delta doping made the threshold voltage roll off a more serious issue, therefore delta doping should be used with caution. The two-dimensional process simulator TSUPREM-4 and the two-dimensional device simulator MEDICI were employed to optimise and design Si/SiGe hybrid CMOS. The output of TSUPREM-4 was transferred automatically to the MEDICI device simulator. This made the simulation results more realistic. For devices at small gate length, lightly doped drain (LDD) structures were required. They would decrease the lateral subdiffusion and allow threshold voltage roll off to be minimised. These structures, however, would generally reduce drain current due to an increase in the series resistance of the drain region. Further consideration must be made of these trade-offs. Comparison between drift diffusion and hydrodynamic simulation results for SiGe p-MOSFETs were presented for the first time, with transport parameters extracted from our in-house full-band hole Monte Carlo transport simulator. It was shown that while drift diffusion and hydrodynamic simulations provided a reasonable estimation of the I-V characteristics for Si devices, the same could not be said for aggressively scaled SiGe devices. The resulting high fields at the source end of the devices meant that nonequilibrium transport effects were significant. Therefore for holes, models based on an isotropic carrier temperature were no longer appropriate, as it was shown by analysing the tensor components of the carrier temperature obtained from Monte Carlo simulation. Two-dimensional drift diffusion and Monte Carlo simulations of well-tempered Si p-MOSFETs with gate lengths of 25 and 50 nm were performed. By comparing Monte Carlo simulations with carefully calibrated drift diffusion results, it was found that nonequilibrium transport was important for understanding the high current device characteristics in sub 0.1 mum p-MOSFETs. The well-tempered devices showed better characteristics than the conventional SiGe devices. Both threshold voltage roll off and the subthreshold slope were acceptable although the effective channel length of this device was reduced from 50 nm to 25 nm. In order to adjust the threshold voltage for the digital CMOS applications, p-type delta doping was used for 50 nm well-tempered SiGe p- MOSFETs. As the delta doping made the threshold voltage roll off too serious, it was not suitable for 25 nm well-tempered SiGe p-MOSFETs

Enhanced velocity overshoot and transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - predictions for deep submicron devices

No abstract avaliable

Validity of the parabolic effective mass approximation in silicon and germanium n-MOSFETs with different crystal orientations

This paper investigates the validity of the parabolic effective mass approximation (EMA), which is almost universally used to describe the size and bias-induced quantization in n-MOSFETs. In particular, we compare the EMA results with a full-band quantization approach based on the linear combination of bulk bands (LCBB) and study the most relevant quantities for the modeling of the mobility and of the on-current of the devices, namely, the minima of the 2-D subbands, the transport masses, and the electron density of states. Our study deals with both silicon and germanium n-MOSFETs with different crystal orientations and shows that, in most cases, the validity of the EMA is quite satisfactory. The LCBB approach is then used to calculate the values of the effective masses that help improve the EMA accuracy. There are crystal orientations, however, where the 2-D energy dispersion obtained by the LCBB method exhibits features that are difficult to reproduce with the EMA model

Gunn Effect in Silicon Nanowires: Charge Transport under High Electric Field

Gunn (or Gunn-Hilsum) Effect and its associated negative differential resistivity (NDR) emanates from transfer of electrons between two different energy bands in a semiconductor. If applying a voltage (electric field) transfers electrons from an energy sub band of a low effective mass to a second one with higher effective mass, then the current drops. This manifests itself as a negative slope or NDR in the I-V characteristics of the device which is in essence due to the reduction of electron mobility. Recalling that mobility is inversely proportional to electron effective mass or curvature of the energy sub band. This effect was observed in semiconductors like GaAs which has direct bandgap of very low effective mass and its second indirect sub band is about 300 meV above the former. More importantly a self-repeating oscillation of spatially accumulated charge carriers along the transport direction occurs which is the artifact of NDR, a process which is called Gunn oscillation and was observed by J. B. Gunn. In sharp contrast to GaAs, bulk silicon has a very high energy spacing (~1 eV) which renders the initiation of transfer-induced NDR unobservable. Using Density Functional Theory (DFT), semi-empirical 10 orbital ($sp^{3}d^{5}s^{*}$) Tight Binding (TB) method and Ensemble Monte Carlo (EMC) simulations we show for the first time that (a) Gunn Effect can be induced in narrow silicon nanowires with diameters of 3.1 nm under 3 % tensile strain and an electric field of 5000 V/cm, (b) the onset of NDR in I-V characteristics is reversibly adjustable by strain and (c) strain can modulate the value of resistivity by a factor 2.3 for SiNWs of normal I-V characteristics i.e. those without NDR. These observations are promising for applications of SiNWs in electromechanical sensors and adjustable microwave oscillators.Comment: 18 pages, 6 figures, 63 reference

Carrier velocity‐field characteristics and alloy scattering potential in Si1−xGex/Si

The alloy scattering potential is an important parameter in SiGe alloys since it not only affects the velocity‐field characteristics for carrier transport, but also allows increased optical transitions by relaxing k‐selection rules. In this letter, we report on the velocity‐field measurements for relaxed and coherently strained SiGe alloys. The alloy scattering potential is obtained from a careful fit to the data. The hole velocity at any field is found to have a bowing behavior as a function of alloy composition. This reflects a strong alloy scattering potential which is calculated to be 0.6 eV for the valence band.  Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/70374/2/APPLAB-63-10-1393-1.pd

Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications

Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3