Low-power low-noise CMOS amplifier for neural recording applications

Journal ArticleThere is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit-the noise efficiency factor-for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5- m CMOS process, passes signals from 0.025 Hz to 7.2 kHz with an input-referred noise of 2.2 Vrms and a power dissipation of 80 W while consuming 0.16 mm2 of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 W while maintaining a similar noise-power tradeoff

Design of integrated circuits to observe brain activity

Journal ArticleThe ability to monitor the simultaneous electrical activity of multiple neurons in the brain enables a wide range of scientific and clinical endeavors. Recent efforts to merge miniature multielectrode neural recording arrays with integrated electronics have revealed significant circuit design challenges. Weak neural signals must be amplified and filtered using low-noise circuits placed close to the electrodes themselves, but power dissipation must strictly be limited to prevent tissue damage due to local heating. In modern recording systems with 100 or more electrodes, raw data rates of 15 Mb/s or more are easily produced. Micropower wireless telemetry circuits cannot transmit information at such high rates, so data reduction must be performed in the implanted device. In this paper, we present integrated circuits and design techniques that address the twin problems of neural signal amplification and data reduction for this severely size- and power-limited application

Integrated circuits for near-infrared biomedical signal acquisition.

Wong, Kak Yeung Alex.Thesis submitted in: November 2007.Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.Includes bibliographical references (leaves 86-89).Abstracts in English and Chinese.Acknowledgement --- p.iAbstract --- p.iii摘要 --- p.vTable of contents --- p.viList of tables --- p.ixList of Figures --- p.xChapter Chapter1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Motivation --- p.1Chapter 1.3 --- Summary of Contributions and Thesis Outline --- p.4Chapter Chapter 2 --- System Design and Architecture --- p.6Chapter 2.1 --- Architectural Consideration --- p.6Chapter 2.1.1 --- Previous work --- p.6Chapter 2.1.2 --- Proposed work --- p.10Chapter A) --- Transimpedance amplifier with off-chip component --- p.10Chapter B) --- Dual-loop transimpedance amplifier --- p.12Chapter 2.2 --- Design consideration for ultra low cutoff frequency filter --- p.13Chapter 2.2.1 --- Previous work on low cutoff frequency filter --- p.14Chapter A) --- GM-C with current division and sub-threshold operation --- p.14Chapter B) --- Capacitance Multiplier --- p.15Chapter C) --- Switched-opamp switched-capacitor (SO-SC) filter --- p.16Chapter 2.2.2 --- Proposed work for the ultra low cutoff frequency filter --- p.17Current steering lowpass filter --- p.17Chapter 2.1 --- Summary --- p.18Chapter Chapter 3 --- Transimpedance Amplifier Design --- p.21Chapter 3.1 --- Transimpedance amplifiEr with off-chip component --- p.21Chapter 3.1.1 --- Transimpedance amplifier with dc photocurrent rejection --- p.21Chapter 3.1.2 --- Proposed solution - Transimpedance amplifier with sample-and-hold in feedback --- p.23Chapter A) --- Operating principle --- p.23Chapter B) --- Simulation results --- p.25Chapter 3.2 --- Dual-loop transimpedance amplifier with DC photocurrent rejection --- p.27Chapter 3.2.1 --- Evolution from basic to proposed work --- p.27Chapter 3.2.2 --- Operating principle --- p.31Chapter 3.2.3 --- Development of the analytic model --- p.32Chapter 3.2.4 --- Derivation of frequency response --- p.37Chapter 3.2.5 --- Noise derivation --- p.40Total input referred noise --- p.43Chapter 3.3 --- Implementation and experimental results --- p.45Chapter 3.3.1 --- Off-chip capacitor TIA --- p.45Measurement results --- p.46Chapter 3.3.2 --- Dual-loop TIA --- p.49Measurement results --- p.51Chapter 3.4 --- Summary and comparison --- p.62Chapter Chapter 4 --- Ultra-Low Cutoff Frequency Filter Design --- p.65Chapter 4.1 --- Current-steering lowpass filter --- p.65Chapter 4.2 --- "Implementation, experimental and measurement results" --- p.67Chapter 4.2.1 --- Measurement results for CS-LPF --- p.68Chapter 4.2.2 --- Measurement results for overall system --- p.75Chapter 4.3 --- Summary --- p.82Chapter Chapter 5 --- Conclusions and Future Work --- p.84Chapter 5.1 --- Conclusions --- p.84Chapter 5.2 --- Future work --- p.85Bibliography --- p.86Appendix A Details about operation --- p.90Appendix B Complex pole derivation --- p.93Appendix C Details about noise derivation --- p.94Appendix D Details about sub-threshold operation --- p.98Appendix E (in CD-ROM) Transfer Function DerivationAppendix F (in CD-ROM) Noise Transfer Function Derivatio

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications

Coherent terahertz radiation with 2.8-octave tunability through chip-scale photomixed microresonator optical parametric oscillation

High spectral purity frequency agile room temperature sources in the terahertz spectrum are foundational elements for imaging, sensing, metrology, and communications. Here we present a chip scale optical parametric oscillator based on an integrated nonlinear microresonator that provides broadly tunable single frequency and multi frequency oscillators in the terahertz regime. Through optical to terahertz down conversion using a plasmonic nanoantenna array, coherent terahertz radiation spanning 2.8 octaves is achieved from 330 GHz to 2.3 THz, with 20 GHz cavity mode limited frequency tuning step and 10 MHz intracavity mode continuous frequency tuning range at each step. By controlling the microresonator intracavity power and pump resonance detuning, tunable multi frequency terahertz oscillators are also realized. Furthermore, by stabilizing the microresonator pump power and wavelength, sub 100 Hz linewidth of the terahertz radiation with 10-15 residual frequency instability is demonstrated. The room temperature generation of both single frequency, frequency agile terahertz radiation and multi frequency terahertz oscillators in the chip scale platform offers unique capabilities in metrology, sensing, imaging and communications

A 129NW Neural Amplifier and Gm-C Filter for EEG Using gm/ID Methodology

This Thesis presents a low-power analog front-end amplifier and Gm-C filter for biomedical sensing applications, specifically for Electroencephalogram (EEG) use. The proposed neural amplifier uses a supply voltage of 1.8V, it has a mid-band gain of 40.75dB, and consumes a total current of 71.82nA, for a total dissipated power of 129.276nW. Also presented is the design of a 3rd order Butterworth Low Pass Gm-C Filter which makes use of 14.7nS transconductors; the proposed filter has a pass band suitable for EEG recording use (1-100Hz). The amplifier and filter utilize current sources without bias resistances which provide 56nA and (1.154nA x 5) respectively. The proposed neural amplifier occupies a chip area of 0.275mm2 in a 0.3μm TSMC process. Simulation of the schematic and extracted chip layout is presented, along with a comparison of similar published works. Finally, a projected power consumption calculation for a multichannel system based on this system is offered

An ultra low power implantable neural recording system for brain-machine interfaces

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 179-187).In the past few decades, direct recordings from different areas of the brain have enabled scientists to gradually understand and unlock the secrets of neural coding. This scientific advancement has shown great promise for successful development of practical brain-machine interfaces (BMIs) to restore lost body functions to patients with disorders in the central nervous system. Practical BMIs require the uses of implantable wireless neural recording systems to record and process neural signals, before transmitting neural information wirelessly to an external device, while avoiding the risk of infection due to through-skin connections. The implantability requirement poses major constraints on the size and total power consumption of the neural recording system. This thesis presents the design of an ultra-low-power implantable wireless neural recording system for use in brain-machine interfaces. The system is capable of amplifying and digitizing neural signals from 32 recording electrodes, and processing the digitized neural data before transmitting the neural information wirelessly to a receiver at a data rate of 2.5 Mbps. By combining state-of-the-art custom ASICs, a commercially-available FPGA, and discrete components, the system achieves excellent energy efficiency, while still offering design flexibility during the system development phase. The system's power consumption of 6.4 mW from a 3.6-V supply at a wireless output data rate of 2.5 Mbps makes it the most energy-efficient implantable wireless neural recording system reported to date. The system is integrated on a flexible PCB platform with dimensions of 1.8 cm x 5.6 cm and is designed to be powered by an implantable Li-ion battery. As part of this thesis, I describe the design of low-power integrated circuits (ICs) for amplification and digitization of the neural signals, including a neural amplifier and a 32-channel neural recording IC. Low-power low-noise design techniques are utilized in the design of the neural amplifier such that it achieves a noise efficiency factor (NEF) of 2.67, which is close to the theoretical limit determined by physics. The neural recording IC consists of neural amplifiers, analog multiplexers, ADCs, serial programming interfaces, and a digital processing unit. It can amplify and digitize neural signals from 32 recording electrodes, with a sampling rate of 31.25 kS/s per channel, and send the digitized data off-chip for further processing. The IC was successfully tested in an in-vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 [mu]W. Such a system is also widely useful in implantable brain-machine interfaces for the blind and paralyzed, and in cochlea implants for the deaf.by Woradorn Wattanapanitch.Ph.D

Probing of Brain States in Real-Time: Introducing the ConSole Environment

Recent years have seen huge advancements in the methods available and used in neuroscience employing EEG or MEG. However, the standard approach is to average a large number of trials for experimentally defined conditions in order to reduce intertrial-variability, i.e., treating it as a source of “noise.” Yet it is now more and more accepted that trial-to-trial fluctuations bear functional significance, reflecting fluctuations of “brain states” that predispose perception and action. Such effects are often revealed in a pre-stimulus period, when comparing response variability to an invariant stimulus. However such offline analyses are disadvantageous as they are correlational by drawing conclusions in a post hoc-manner and stimulus presentation is random with respect to the feature of interest. A more direct test is to trigger stimulus presentation when the relevant feature is present. The current paper introduces Constance System for Online EEG (ConSole), a software package capable of analyzing ongoing EEG/MEG in real-time and presenting auditory and visual stimuli via internal routines. Stimulation via external devices (e.g., transcranial magnetic stimulation) or third-party software (e.g., PsyScope X) is possible by sending TTL-triggers. With ConSole it is thus possible to target the stimulation at specific brain states. In contrast to many available applications, ConSole is open-source. Its modular design enhances the power of the software as it can be easily adapted to new challenges and writing new experiments is an easy task. ConSole is already pre-equipped with modules performing standard signal processing steps. The software is also independent from the EEG/MEG system, as long as a driver can be written (currently two EEG systems are supported). Besides a general introduction, we present benchmark data regarding performance and validity of the calculations used, as well as three example applications of ConSole in different settings. ConSole can be downloaded at: http://console-kn.sf.net

Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 µW and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 µVrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd