Scheduling Analysis from Architectural Models of Embedded Multi-Processor Systems

International audienceAs embedded systems need more and more computing power, many products require hardware platforms based on multiple processors. In case of real-time constrained systems, the use of scheduling analysis tools is mandatory to validate the design choices, and to better use the processing capacity of the system. To this end, this paper presents the extension of the scheduling analysis tool Cheddar to deal with multi-processor schedul- ing. In a Model Driven Engineering approach, useful infor- mation about the scheduling of the application is extracted from a model expressed with an architectural language called AADL. We also define how the AADL model must be writen to express the standard policies for the multi-processor scheduling

Enabling Traceability in an MDE Approach to Improve Performance of GPU Applications

Graphics Processor Units (GPUs) are known for offering high per- formance and power efficiency for processing algorithms that suit well to their massively parallel architecture. Unfortunately, as parallel programming for this kind of architecture requires a complex distribution of tasks and data, developers find it difficult to implement their applications effectively. Although approaches based on source-to-source and model-to-source transformations have intended to provide a low learning curve for parallel programming and take advantage of architecture features to create optimized applications, the programming re- mains difficult for neophytes. A Model Driven Engineering (MDE) approach for GPU intends to hide the low-level details of GPU programming by automati- cally generating the application from the high-level specifications. However, the application designer should take into account some adjustments in the source code to achieve better performance at runtime. Directly modifying the gen- erated source code goes against the MDE philosophy. Moreover, the designer does not necessarily have the required knowledge to effectively modify the GPU generated code. This work aims at improving performance by returning to the high-level models, specific execution data from a profiling tool enhanced by smart advices from an analysis engine. In order to keep the link between exe- cution and model, the process is based on a traceability mechanism. Once the model is automatically annotated, it can be re-factored by aiming performance on the re-generated code. Hence, this work allows us keeping coherence between model and code without forgetting to harness the power of GPUs. To illustrate and clarify key points of this approach, an experimental example taking place in a transformation chain from UML-MARTE models to OpenCL code is provided.Graphics Processor Units (GPU) sont connus pour offrir de hautes performances et d'efficacité énergétique pour les algorithmes de traitement qui conviennent bien à leur architecture massivement paralléle. Malheureusement, comme la programmation paralléle pour ce type d'architecture exige une distribution complexe des tâches et des données, les développeurs ont des difficultés à mettre en oeuvre leurs applications de manière efficace. Bien que les approches basées sur les transformations source-to-source et model-to-source ont pour but de fournir une basse courbe d'apprentissage pour la programmation paralléle et tirer parti des fonctionnalités de l'architecture pour créer des applications optimisées, la programmation demeure difficile pour les néophytes. Une approche Model Driven Engineering (MDE) pour le GPU a l'intention de cacher les détails de bas niveau de la programmation GPU en générant automatiquement l'application à partir des spécifications de haut niveau. Cependant, le concepteur de l'application devrait tenir compte de certains ajustements dans le code source pour obtenir de meilleures performances à l'exécution. Modifiant directement le code source généré ne fait pas partie de la philosophie MDE. Par ailleurs, le concepteur n'a pas forcément les connaissances requises pour modifier efficacement le code généré par le GPU. Ce travail vise à améliorer la performance en revenant aux modèles de haut niveau, les données d'exécution spécifiques à partir d'un outil de profilage améliorée par des conseils intelligents d'un moteur d'analyse. Afin de maintenir le lien entre l'exécution et le modèle, le processus est basé sur un mécanisme de traçabilité. Une fois le modèle est automatiquement annoté, il peut être repris en visant la performance sur la réutilisation du code généré. Ainsi, ce travail nous permet de garder la cohérence entre le modèle et le code sans oublier d'exploiter la puissance des GPU. Afin d'illustrer et de clarifier les points clés de cette approche, nous fournissons un exemple se déroule dans une chaîne de transformation à partir de modéles UML- MARTE au code OpenCL

From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation *

International audienceOur objective is to facilitate the development of complex time-triggered systems by automating the allocation and scheduling steps. We show that full automation is possible while taking into account the elements of complexity needed by a complex embedded control system. More precisely, we consider deterministic functional specifications provided (as often in an industrial setting) by means of synchronous data-flow models with multiple modes and multiple relative periods. We first extend this functional model with an original real-time characterization that takes advantage of our time-triggered framework to provide a simpler representation of complex end-to-end flow requirements. We also extend our specifications with additional non-functional properties specifying partitioning, allocation , and preemptability constraints. Then, weprovide novel algorithms for the off-line scheduling of these extended specifications onto partitioned time-triggered architectures à la ARINC 653. The main originality of our work is that it takes into account at the same time multiple complexity elements: various types of non-functional properties (real-time, partitioning, allocation, preemptability) and functional specifications with conditional execution and multiple modes. Allocation of time slots/windows to partitions can be fullyor partially provided, or synthesized by our tool. Our algorithms allow the automatic allocation and scheduling onto multi-processor (distributed) sys-tems with a global time base, taking into account communication costs. We demonstrate our technique on a model of space flight software systemwith strong real-time determinism requirements

Analysis and simulation of scheduling techniques for real-time embedded multi-core architectures

In this modern era of technological progress, multi-core processors have brought significant and consequential improvements in the available processing potential to the world of real-time embedded systems. These improvements impose a rapid increment of software complexity as well as processing demand placed on the underlying hardware. As a consequence, the need for efficient yet predictable multi-core scheduling techniques is on the rise. As part of this thesis, in-depth research of currently available multi-core scheduling techniques, belonging to both partitioned and global approaches, is done in the context of real-time embedded systems. The emphasis is on the degree of their usability on hard real-time systems, focusing on the scheduling techniques offering better processor affinity and the lower number of context switching. Also, an extensive research of currently available real-time test-beds as well as real-time operating systems is performed. Finally, a subset of the analyzed multi-core scheduling techniques comprising PSN-EDF, GSN-EDF, PD$^{2}$ and PD$^{2*}$ is simulated on the real-time test-bed LITMUS$^{RT}$

Integrating Profiling into MDE Compilers

International audienceScientific computation requires more and more performance in its algorithms. New massively parallel architectures suit well to these algorithms. They are known for offering high performance and power efficiency. Unfortunately, as parallel programming for these architectures requires a complex distribution of tasks and data, developers find difficult to implement their applications effectively. Although approaches based on source-to-source intends to provide a low learning curve for parallel programming and take advantage of architecture features to create optimized applications, programming remains difficult for neophytes. This work aims at improving performance by returning to the high-level models, specific execution data from a profiling tool enhanced by smart advices computed by an analysis engine. In order to keep the link between execution and model, the process is based on a traceability mechanism. Once the model is automatically annotated, it can be re-factored aiming better performances on the re-generated code. Hence, this work allows keeping coherence between model and code without forgetting to harness the power of parallel architectures. To illustrate and clarify key points of this approach, we provide an experimental example in GPUs context. The example uses a transformation chain from UML-MARTE models to OpenCL code

On the automated compilation of UML notation to a VLIW chip multiprocessor

With the availability of more and more cores within architectures the process of extracting implicit and explicit parallelism in applications to fully utilise these cores is becoming complex. Implicit parallelism extraction is performed through the inclusion of intelligent software and hardware sections of tool chains although these reach their theoretical limit rather quickly. Due to this the concept of a method of allowing explicit parallelism to be performed as fast a possible has been investigated. This method enables application developers to perform creation and synchronisation of parallel sections of an application at a finer-grained level than previously possible, resulting in smaller sections of code being executed in parallel while still reducing overall execution time. Alongside explicit parallelism, a concept of high level design of applications destined for multicore systems was also investigated. As systems are getting larger it is becoming more difficult to design and track the full life-cycle of development. One method used to ease this process is to use a graphical design process to visualise the high level designs of such systems. One drawback in graphical design is the explicit nature in which systems are required to be generated, this was investigated, and using concepts already in use in text based programming languages, the generation of platform-independent models which are able to be specialised to multiple hardware architectures was developed. The explicit parallelism was performed using hardware elements to perform thread management, this resulted in speed ups of over 13 times when compared to threading libraries executed in software on commercially available processors. This allowed applications with large data dependent sections to be parallelised in small sections within the code resulting in a decrease of overall execution time. The modelling concepts resulted in the saving of between 40-50% of the time and effort required to generate platform-specific models while only incurring an overhead of up to 15% the execution cycles of these models designed for specific architectures

Developing critical embedded systems on multicore architectures: the Prelude-SchedMCore toolset

International audienceIn this paper we present an end-to-end framework for the design and the implementation of embedded systems on a symmetric multicore. The developer first specifies the system using the \prelude language, a formal real-time architecture description language. The Prelude compiler then translates the program into a set of communicating periodic tasks that preserves the semantics of the original program. The schedulability analysis is performed by the SchedMCore analyzer. If the program is schedulable, it can finally be executed on the target multicore architecture using the \schedmcore execution environment

MARTE based design approach for targeting Reconfigurable Architectures

International audienceThis paper demonstrates the use of a model driven design flow for Multiprocessor System on chips (MPSoCs) such as those dedicated to intensive signal processing applications. Due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. This paper addresses this issue and proposes a novel SoC codesign methodology based on Model Driven Engineering (MDE) and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by OMG (Object Management Group), in order to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs

Combining Time-Triggered Plans with Priority Scheduled Task Sets

The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-319-39083-3_13Time-triggered and concurrent priority-based scheduling are the two major approaches in use for real-time and embedded systems. Both approaches have their own advantages and drawbacks. On the one hand, priority-based systems facilitate separation of concerns between functional and timing requirements by relying on an underlying real- time operating system that takes all scheduling decisions at run time. But this is at the cost of indeterminism in the exact timing pattern of execution of activities, namely variable release jitter. On the other hand, time-triggered schedules are more intricate to design since all schedul- ing decisions must be taken beforehand in the design phase, but their advantage is determinism and more chances for minimisation of release jitter. In this paper we propose a software architecture that enables the combined and controlled execution of time-triggered plans and priority- scheduled tasks. We also describe the implementation of an Ada library supporting it. Our aim is to take advantage of the best of both ap- proaches by providing jitter-controlled execution of time-triggered tasks (e.g., control tasks), coexisting with a set of priority-scheduled tasks, with less demanding jitter requirements.This work has been partly supported by the Spanish Government’s project M2C2 (TIN2014-56158-C4-1-P-AR) and the European Commission’s project EMC2 (ARTEMIS-JU Call 2013 AIPP-5, Contract 621429).Real Sáez, JV.; Sáez Barona, S.; Crespo, A. (2016). Combining Time-Triggered Plans with Priority Scheduled Task Sets. En Reliable Software Technologies – Ada-Europe 2016. Springer. 195-212. https://doi.org/10.1007/978-3-319-39083-3_13S195212Liu, C., Layland, J.: Scheduling algorithms for multiprogramming in a hard real-time environment. J. ACM 20(1), 46–61 (1973)Martí, P., Fuertes, J., Fohler, G.: Jitter compensation for real-time control systems. In: Real-Time Systems Symposium (2001)Dobrin, R.: Combining off-line schedule construction and fixed priority scheduling in real-time computer systems. Ph.D. thesis. Mälardalen University (2005)Cervin, A.: Integrated control and real-time scheduling. Ph.D. thesis. Lund Institute of Technology, April 2003Balbastre, P., Ripoll, I., Vidal, J., Crespo, A.: A task model to reduce control delays. Real-Time Syst. 27(3), 215–236 (2004)Hong, S., Hu, X., Lemmon, M.: Reducing delay jitter of real-time control tasks through adaptive deadline adjustments. In: 22nd Euromicro Conference on Real-Time Systems - ECRTS, pp. 229–238. IEEE Computer Society (2010)ISO/IEC-JTC1-SC22-WG9: Ada Reference Manual ISO/IEC 8652:2012(E) (2012). http://www.ada-europe.org/manuals/LRM-2012.pdfBaker, T.P., Shaw, A.: The cyclic executive model and Ada. In: Proceedings IEEE Real Time Systems Symposium 1988, Huntsville, Alabama, pp. 120–129 (1988)Liu, J.W.S.: Real-Time Systems. Prentice-Hall Inc., Upper Saddle River (2000)Pont, M.J.: The Engineering of Reliable Embedded Systems: LPC1769. SafeTTy Systems Limited, Skelmersdale (2014). ISBN: 978-0-9930355-0-0Aldea Rivas, M., González Harbour, M.: MaRTE OS: an Ada kernel for real-time embedded applications. In: Strohmeier, A., Craeynest, D. (eds.) Ada-Europe 2001. LNCS, vol. 2043, pp. 305–316. Springer, Heidelberg (2001)Palencia, J., González-Harbour, M.: Schedulability analysis for tasks with static and dynamic offsets. In: 9th IEEE Real-Time Systems Symposium (1998)Wellings, A.J., Burns, A.: A framework for real-time utilities for Ada 2005. Ada Lett. XXVI XXVII(2), 41–47 (2007)Real, J., Crespo, A.: Incorporating operating modes to an Ada real-time framework. Ada Lett. 30(1), 73–85 (2010)Sáez, S., Terrasa, S., Crespo, A.: A real-time framework for multiprocessor platforms using Ada 2012. In: Romanovsky, A., Vardanega, T. (eds.) Ada-Europe 2011. LNCS, vol. 6652, pp. 46–60. Springer, Heidelberg (2011