CMOS radio frequency circuits for short-range direct-conversion receivers

The research described in this thesis is focused on the design and implementation of radio frequency (RF) circuits for direct-conversion receivers. The main interest is in RF front-end circuits, which contain low-noise amplifiers, downconversion mixers, and quadrature local oscillator signal generation circuits. Three RF front-end circuits were fabricated in a short-channel CMOS process and experimental results are presented. A low-noise amplifier (LNA) is typically the first amplifying block in the receiver. A large number of LNAs have been reported in the literature. In this thesis, wideband LNA structures are of particular interest. The most common and relevant LNA topologies are analyzed in detail in the frequency domain and theoretical limitations are found. New LNA structures are presented and a comparison to the ones found in the literature is made. In this work, LNAs are implemented with downconversion mixers as RF front-ends. The designed mixers are based on the commonly used Gilbert cell. Different mixer implementation alternatives are presented and the design of the interface between the LNA and the downconversion mixer is discussed. In this work, the quadrature local oscillator signal is generated either by using frequency dividers or polyphase filters (PPF). Different possibilities for implementing frequency dividers are briefly described. Polyphase filters were already introduced by the 1970s and integrated circuit (IC) realizations to generate quadrature signals have been published since the mid-1990s. Although several publications where the performance of the PPFs has been studied either by theoretical calculations or simulations can be found in the literature, none of them covers all the relevant design parameters. In this thesis, the theory behind the PPFs is developed such that all the relevant design parameters needed in the practical circuit design have been calculated and presented with closed-form equations whenever possible. Although the main focus was on twoand three-stage PPFs, which are the most common ones encountered in practical ICs, the presented calculation methods can be extended to analyze the performance of multistage PPFs as well. The main application targets of the circuits presented in this thesis are the short-range wireless sensor system and ultrawideband (UWB). Sensors are capable of monitoring temperature, pressure, humidity, or acceleration, for example. The amount of transferred data is typically small and therefore a modest bit rate, less than 1 Mbps, is adequate. The sensor system applied in this thesis operates at 2.4-GHz ISM band (Industrial, Scientific, and Medical). Since the sensors must be able to operate independently for several years, extremely low power consumption is required. In sensor radios, the receiver current consumption is dominated by the blocks and elements operating at the RF. Therefore, the target was to develop circuits that can offer satisfactory performance with a current consumption level that is small compared to other receivers targeted for common cellular systems. On the other hand, there is a growing need for applications that can offer an extremely high data rate. UWB is one example of such a system. At the moment, it can offer data rates of up to 480 Mbps. There is a frequency spectrum allocated for UWB systems between 3.1 and 10.6 GHz. The UWB band is further divided into several narrower band groups (BG), each occupying a bandwidth of approximately 1.6 GHz. In this work, a direct-conversion RF front-end is designed for a dual-band UWB receiver, which operates in band groups BG1 and BG3, i.e. at 3.1 – 4.8 GHz and 6.3 – 7.9 GHz frequency areas, respectively. Clearly, an extremely wide bandwidth combined with a high operational frequency poses challenges for circuit design. The operational bandwidths and the interfaces between the circuit blocks need to be optimized to cover the wanted frequency areas. In addition, the wideband functionality should be achieved without using a number of on-chip inductors in order to minimize the die area, and yet the power consumption should be kept as small as possible. The characteristics of the two main target applications are quite different from each other with regard to power consumption, bandwidth, and operational frequency requirements. A common factor for both is their short, i.e. less than 10 meters, range. Although the circuits presented in this thesis are targeted on the two main applications mentioned above, they can be utilized in other kind of wireless communication systems as well. The performance of three experimental circuits was verified with measurements and the results are presented in this work. Two of them have been a part of a whole receiver including baseband amplifiers and filters and analog-to-digital converters. Experimental circuits were fabricated in a 0.13-µm CMOS process. In addition, this thesis includes design examples where new circuit ideas and implementation possibilities are introduced by using 0.13-µm and 65-nm CMOS processes. Furthermore, part of the theory presented in this thesis is validated with design examples in which actual IC component models are used.Tässä väitöskirjassa esitetty tutkimus keskittyy suoramuunnosvastaanottimen radiotaajuudella (radio frequency, RF) toimivien piirien suunnitteluun ja toteuttamiseen. Työ keskittyy vähäkohinaiseen vahvistimeen (low-noise amplifier, LNA), alassekoittajaan ja kvadratuurisen paikallisoskillaattorisignaalin tuottavaan piiriin. Työssä toteutettiin kolme RF-etupäätä erittäin kapean viivanleveyden CMOS-prosessilla, ja niiden kokeelliset tulokset esitetään. Vähäkohinainen vahvistin on yleensä ensimmäinen vahvistava lohko vastaanottimessa. Useita erilaisia vähäkohinaisia vahvistimia on esitetty kirjallisuudessa. Tämän työn kohteena ovat eritoten laajakaistaiset LNA-rakenteet. Tässä työssä analysoidaan taajuustasossa yleisimmät ja oleellisimmat LNA-topologiat. Lisäksi uusia LNA-rakenteita on esitetty tässä työssä ja niitä on verrattu muihin kirjallisuudessa esitettyihin piireihin. Tässä työssä LNA:t on toteutettu yhdessä alassekoittimen kanssa muodostaen RF-etupään. Työssä suunnitellut alassekoittimet perustuvat yleisesti käytettyyn Gilbertin soluun. Erilaisia sekoittajan suunnitteluvaihtoehtoja ja LNA:n ja alassekoittimen välisen rajapinnan toteutustapoja on esitetty. Tässä työssä kvadratuurinen paikallisoskillaattorisignaali on muodostettu joko käyttämällä taajuusjakajia tai monivaihesuodattimia. Erilaisia taajuusjakajia ja niiden toteutustapoja käsitellään yleisellä tasolla. Monivaihesuodatinta, joka on alunperin kehitetty jo 1970-luvulla, on käytetty integroiduissa piireissä kvadratuurisignaalin tuottamiseen 1990-luvun puolivälistä lähtien. Kirjallisuudesta löytyy lukuisia artikkeleita, joissa monivaihesuodattimen toimintaa on käsitelty teoreettisesti laskien ja simuloinnein. Kuitenkaan kaikkia sen suunnitteluparametreja ei tähän mennessä ole käsitelty. Tässä työssä monivaihesuodattimen teoriaa on kehitetty edelleen siten, että käytännön piirisuunnittelussa tarvittavat oleelliset parametrit on analysoitu ja suunnitteluyhtälöt on esitetty suljetussa muodossa aina kuin mahdollista. Vaikka työssä on keskitytty yleisimpiin eli kaksi- ja kolmiasteisiin monivaihesuodattimiin, on työssä esitetty menetelmät, joilla laskentaa voidaan jatkaa aina useampiasteisiin suodattimiin asti. Työssä esiteltyjen piirien pääkohteina ovat lyhyen kantaman sensoriradio ja erittäin laajakaistainen järjestelmä (ultrawideband, UWB). Sensoreilla voidaan tarkkailla esimerkiksi ympäristön lämpötilaa, kosteutta, painetta tai kiihtyvyyttä. Siirrettävän tiedon määrä on tyypillisesti vähäistä, jolloin pieni tiedonsiirtonopeus, alle 1 megabitti sekunnissa, on välttävä. Tämän työn kohteena oleva sensoriradiojärjestelmä toimii kapealla kaistalla 2,4 gigahertsin ISM-taajuusalueella (Industrial, Scientific, and Medical). Koska sensorien tavoitteena on toimia itsenäisesti ilman pariston vaihtoa useita vuosia, täytyy niiden kuluttaman virran olla erittäin vähäistä. Sensoriradiossa vastaanottimen tehonkulutuksen kannalta määräävässä asemassa ovat radiotaajuudella toimivat piirit. Tavoitteena oli tutkia ja kehittää piirirakenteita, joilla päästään tyydyttävään suorituskykyyn tehonkulutuksella, joka on vähäinen verrattuna muiden tavallisten langattomien tiedonsiirtojärjestelmien radiovastaanottimiin. Toisaalta viime aikoina on kasvanut tarvetta myös järjestelmille, jotka kykenevät tarjoamaan erittäin korkean tiedonsiirtonopeuden. UWB on esimerkki tällaisesta järjestelmästä. Tällä hetkellä se tarjoaa tiedonsiirtonopeuksia aina 480 megabittiin sekunnissa. UWB:lle on varattu taajuusalueita 3,1 ja 10,6 gigahertsin taajuuksien välillä. Kyseinen kaista on edelleen jaettu pienempiin taajuusryhmiin (band group, BG), joiden kaistanleveys on noin 1,6 gigahertsiä. Tässä työssä on toteutettu RF-etupää radiovastaanottimeen, joka pystyy toimimaan BG1:llä ja BG3:lla eli taajuusalueilla 3,1 - 4,7 GHz ja 6,3 - 7,9 GHz. Erittäin suuri kaistanleveys yhdistettynä korkeaan toimintataajuuteen tekee radiotaajuuspiirien suunnittelusta haasteellista. Piirirakenteiden toimintakaistat ja piirien väliset rajapinnat tulee optimoida riittävän laajoiksi käyttämättä kuitenkaan liian montaa piille integroitua kelaa piirin pinta-alan minimoimiseksi, ja lisäksi piirit tulisi toteuttaa mahdollisimman alhaisella tehonkulutuksella. Työssä esiteltyjen piirien kaksi pääkohdetta ovat hyvin erityyppisiä, mitä tulee tehonkulutus-, kaistanleveys- ja toimintataajuusvaatimuksiin. Yhteistä molemmille on lyhyt, alle 10 metrin kantama. Vaikka tässä työssä esitellyt piirit onkin kohdennettu kahteen pääsovelluskohteeseen, voidaan esitettyjä piirejä käyttää myös muiden tiedonsiirtojärjestelmien piirien suunnitteluun. Tässä työssä esitetään mittaustuloksineen yhteensä kolme kokeellista piiriä yllämainittuihin järjestelmiin. Kaksi ensimmäistä kokeellista piiriä muodostaa kokonaisen radiovastaanottimen yhdessä analogisten kantataajuusosien ja analogia-digitaali-muuntimien kanssa. Esitetyt kokeelliset piirit on toteutettu käyttäen 0,13 µm:n viivanleveyden CMOS-tekniikkaa. Näiden lisäksi työ pitää sisällään piirisuunnitteluesimerkkejä, joissa esitetään ideoita ja mahdollisuuksia käyttäen 0,13 µm:n ja 65 nm:n viivanleveyden omaavia CMOS-tekniikoita. Lisäksi piirisuunnitteluesimerkein havainnollistetaan työssä esitetyn teorian paikkansapitävyyttä käyttämällä oikeita komponenttimalleja.reviewe

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

Integration of broadband direct-conversion quadrature modulators

To increase spectral efficiency, transmitters usually send only one of the information carrying sidebands centered around a single radio-frequency carrier. The close-lying mirror, or image, sideband will be eliminated either by the filtering method or by the phasing method. Since filter Q-values rise in direct relation to the transmitted frequencies, the filtering method is generally not feasible for integrated microwave transmitters. A quadrature modulator realizes the phasing method by combining signals phased at quadrature (i.e. at 90° offsets) to produce a single-sideband (SSB) output. In this way output filtering can be removed or its specifications greatly relieved so as to produce an economical microwave transmitter. The proliferation of integrated circuit (IC) technologies since the 1980s has further boosted the popularity of quadrature modulator as an IC realization makes possible the economical production of two closely matched doubly balanced mixers, which suppress carrier and even-order spurious leakage to circuit output. Another strength of IC is its ability to perform microwave quadrature generation accurately on-chip, and thereby to avoid most of the interconnect parasitics which could ruin high-frequency quadrature signaling. Nevertheless, all quadrature modulator implementations are sensitive to phasing and amplitude errors, which are born as a result of mismatches, from the use of inaccurate differential signaling, and from inadequacies in the phasing circuitry itself. A 2° phase error is easily produced, and it reduces the image-rejection ratio (IRR) to −30 dBc. Therefore, as baseband signals synthesized by digital signal processing (DSP) are sufficiently accurate, this thesis concentrates on analyzing and producing the microwave signal path of a direct-conversion quadrature modulator with special emphasis on broadband, multimode radio-compatible operation. A model of the direct-conversion quadrature modulator operation has been developed, which reveals the effect the circuit non-linearities and mismatch-related offsets have on available performance. Further, theoretical proof is given of the well-known property of improving differential signal balance that cascaded differential pairs exhibit. Among the practical results, a current reuse mixer has been developed, which improves the transmitted signal-to-noise-ratio (SNR) by 3 dB, with a maximum measured dynamic range of +158 dB. The complementary bipolar process was further used to extend the bipolar push-pull stage bandwidth to 9.5 GHz. At the core of this work is the parallel switchable polyphase (PP) filter quadrature generator that was developed, since it makes possible accurate broadband IQ generation without the high loss that usually results from the application of PP filtering. Two IQ modulator prototypes were realized to test simulated and theoretically derived data: the 0.8 µm SiGe IC achieves an IRR better than −40 dBc over 0.75-3.6 GHz, while the 0.13 µm digital bulk CMOS IC achieves better than −37 dBc over 0.56-4.76 GHz. For this IRR performance the SiGe prototype boasts the inexpensive solution of integrated baluns, while the CMOS one utilizes a coil-transmission line hybrid transformer at its LO input to drive the switchable PP filters.Taajuuksien käytön tehostamiseksi lähettimet lähettävät yleensä vain toisen informaatiota sisältävistä sivukaistoistaan yhdelle radiotaajuuksiselle kantoaallolle keskitettynä. Viereinen peilitaajuus eli sivukaista vaimennetaan joko suodattamalla tai vaiheistamalla signalointia sopivasti. Koska suodattimen hyvyysluvut nousevat suorassa suhteessa käytettyyn taajuuteen, ei suodatusmenetelmä ole yleensä mahdollinen mikroaaltotaajuusalueen lähettimissä. Kvadratuurimodulaattori toteuttaa vaiheistusmenetelmän yhdistämällä 90-asteen vaihesiirroksin vaiheistetut signaalit yksisivukaistaisen lähetteen tuottamiseksi. Näin voidaan korvata lähdön suodatus joko kokonaan tai lieventämällä vaadittavia suoritusarvoja, jolloin mikroaaltoalueen lähetin voidaan tuottaa taloudellisesti. Integroitujen piiriratkaisujen yleistyminen 1980-luvulta lähtien on edesauttanut kvadratuurimodulaattorin suosiota, koska integroidulle piirille voidaan taloudellisesti tuottaa kaksi hyvin ominaisuuksiltaan toisiaan vastaavaa kaksoisbalansoitua sekoitinta, ja nämä tunnetusti vaimentavat kantoaaltovuotoa ja parillisia harmoonisia piirin lähdössä. Toinen integroitujen piirien vahvuus on kyky tarkkaan mikroaaltoalueen kvadratuurisignalointiin samalla piirillä, jolloin vältetään suurin osa kytkentöjen parasiittisista jotka muutoin voisivat tuhota korkeataajuuksisen 90-asteen vaiheistuksen. Kaikki kvadratuurimodulaattorit ovat joka tapauksessa herkkiä vaiheistus- ja amplitudieroille, joita syntyy komponenttiarvojen satunnaishajonnasta, epätarkan differentiaalisen signaloinnin käytöstä, ja itse vaiheistuspiiristön puutteellisuuksista. Kahden asteen vaihevirhe syntyy helposti, ja tällöin sivukaistavaimennus heikkenee -30 dBc:n tasolle. Tämänvuoksi, ja olettaen että digitaalisella signaaliprosessorilla luotu kantataajuuksinen signalointi on riittävän tarkkaa, tämä väitöskirja keskittyy kvadratuurimodulaattorin mikroaaltotaajuuksisen signaalipolun analysointiin ja tuottamiseen painottaen erityisesti laajakaistaista, monisovellusradioiden kanssa yhteensopivaa toimivuutta. Kvadratuurimodulaattorin toimintamallia on kehitetty siten, että mallissa huomioidaan epälineaarisuuksien ja piirielementtien satunnaishajontojen vaikutus saavutettavalle suorituskyvylle. Lisäksi on teoreettisesti todistettu sinänsä hyvin tunnettu peräkkäin kytkettyjen vahvistinasteiden differentiaalisen signaloinnin symmetrisyyttä parantava vaikutus. Käytännön tuloksista voidaan mainita kehitetty virtaakierrättävä sekoitin, joka parantaa signaali-kohinasuhdetta +3 dB, suurimman mitatun dynaamisen alueen ollessa +158 dB. Samaa komplementaarista bipolaariprosessia käytettiin edelleen bipolaarisen vuorovaihe-asteen kaistan levittämisessä 9.5 GHz:iin. Yhtenä tämän työn tärkeimmistä tuloksista on kehitetty kytkimin valittavista rinnakkaisista monivaihesuodattimista koostuva kvadratuurigeneraattori, jolla on mahdollista tuottaa laajakaistaista IQ-signalointia ilman suurta häviötä joka yleensä liittyy monivaihesuodattimien käyttöön. Kaksi IQ-modulaattoriprototyyppiä toteutettiin simuloitujen ja teoreettisesti mallinnettujen tulosten testaamiseksi: 0.8 µm SiGe integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -40 dBc yli 0.75-3.6 GHz, kun taas 0.13 µm digitaalipiirien tuottamiseen tarkoitetulla CMOS prosessilla toteutettu integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -37 dBc taajuusalueella 0.56-4.76 GHz. Näihin sivukaistavaimennuksiin SiGe prototyyppi pääsee edullisesti integroiduin symmetrointimuuntajin, kun taas CMOS piirillä käytetään kela-siirtojohto-tyyppistä yhdistelmämuuntajaa LO-sisääntulossa josta ajetaan erikseen kytkettäviä monivaihesuodattimia.reviewe

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

A low power, low noise, 1.8 GHz voltage-controlled oscillator

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaf 97).by Donald A. Hitko.M.S