Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop

This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

Autonomous smart antenna systems for future mobile devices

Along with the current trend of wireless technology innovation, wideband, compact size, low-profile, lightweight and multiple functional antenna and array designs are becoming more attractive in many applications. Conventional wireless systems utilise omni-directional or sectored antenna systems. The disadvantage of such antenna systems is that the electromagnetic energy, required by a particular user located in a certain direction, is radiated unnecessarily in every direction within the entire cell, hence causing interference to other users in the system. In order to limit this source of interference and direct the energy to the desired user, smart antenna systems have been investigated and developed. This thesis presents the design, simulation, fabrication and full implementation of a novel smart antenna system for future mobile applications. The design and characterisation of a novel antenna structure and four-element liner array geometry for smart antenna systems are proposed in the first stage of this study. Firstly, a miniaturised microstrip-fed planar monopole antenna with Archimedean spiral slots to cover WiFi/Bluetooth and LTE mobile applications has been demonstrated. The fundamental structure of the proposed antenna element is a circular patch, which operates in high frequency range, for the purpose of miniaturising the circuit dimension. In order to achieve a multi-band performance, Archimedean spiral slots, acting as resonance paths, have been etched on the circular patch antenna. Different shapes of Archimedean spiral slots have been investigated and compared. The miniaturised and optimised antenna achieves a bandwidth of 2.2GHz to 2.9GHz covering WiFi/Bluetooth (2.45GHz) and LTE (2.6GHz) mobile standards. Then a four-element linear antenna array geometry utilising the planar monopole elements with Archimedean spiral slots has been described. All the relevant parameters have been studied and evaluated. Different phase shifts are excited for the array elements, and the main beam scanning range has been simulated and analysed. The second stage of the study presents several feeding network structures, which control the amplitude and phase excitations of the smart antenna elements. Research begins with the basic Wilkinson power divider configuration. Then this thesis presents a compact feeding network for circular antenna array, reconfigurable feeding networks for tuning the operating frequency and polarisations, a feeding network on high resistivity silicon (HRS), and an ultrawide-band (UWB) feeding network covering from 0.5GHz to 10GHz. The UWB feeding network is used to establish the smart antenna array system. Different topologies of phase shifters are discussed in the third stage, including ferrite phase shifters and planar phase shifters using switched delay line and loaded transmission line technologies. Diodes, FETs, MMIC and MEMS are integrated into different configurations. Based on the comparison, a low loss and high accurate Hittite MMIC analogue phase shifter has been selected and fully evaluated for this implementation. For the purpose of impedance matching and field matching, compact and ultra wideband CPW-to-Microstrip transitions are utilised between the phase shifters, feeding network and antenna elements. Finally, the fully integrated smart antenna array achieves a 10dB reflection coefficient from 2.25GHz to 2.8GHz, which covers WiFi/Bluetooth (2.45GHz) and LTE (2.6GHz) mobile applications. By appropriately controlling the voltage on the phase shifters, the main beam of the antenna array is steered ±50° and ±52°, for 2.45GHz and 2.6GHz, respectively. Furthermore, the smart antenna array demonstrates a gain of 8.5dBi with 40° 3dB bandwidth in broadside direction, and has more than 10dB side lobe level suppression across the scan. The final stage of the study investigates hardware and software automatic control systems for the smart antenna array. Two microcontrollers PIC18F4550 and LPC1768 are utilised to build the control PCBs. Using the graphical user interfaces provided in this thesis, it is able to configure the beam steering of the smart antenna array, which allows the user to analyse and optimise the signal strength of the received WiFi signals around the mobile device. The design strategies proposed in this thesis contribute to the realisation of adaptable and autonomous smart phone systems

Distributed antenna system using sigma-delta intermediate-frequency-over-fiber for frequency bands above 24 GHz

The fifth generation (5G) cellular network is expected to include the millimeter wave spectrum, to increase base station density, and to employ higher-order multiple-antenna technologies. The centralized radio access network architectures combined with radio-over-fiber (RoF) links can be the key enabler to improve fronthaul networks. The sigma-delta modulated signal over fiber (SDoF) architecture has been proposed as a solution leveraging the benefits of both digitized and analog RoF. This work proposes a novel distributed antenna system using sigma-delta modulated intermediate-frequency signal over fiber (SDIFoF) links. The system has an adequately good optical bit-rate efficiency and high flexibility to switch between different carrier frequencies. The SDIFoF link transmits a signal centered at a 2.5 GHz intermediate frequency over a 100 m multi-mode fiber and the signal is up-converted to the radio frequency (24-29 GHz) at the remote radio unit. An average error vector magnitude (EVM) of 6.40% (-23.88 dB) is achieved over different carrier frequencies when transmitting a 300 MHz-bandwidth 64-QAM OFDM signal. The system performance is demonstrated by a 2 x 1 multiple-input single-output system transmitting 160 MHz-bandwidth 64-QAM OFDM signals centered at 25 GHz. Owing to transmit diversity, an average gain of 1.12 dB in EVM is observed. This work also evaluates the performance degradation caused by asynchronous phase noise between remote radio units. The performance shows that the proposed approach is a competitive solution for the 5G downlink fronthaul network for frequency bands above 24 GHz

Ultra wideband communication link

Ultra-wideband communication (UWB) has been a topic of extensive research in recent years especially for its short-range communication and indoor applications. The preliminary objective of the project was to develop a description and understanding of the basic components of the communication link at microwave frequencies in order to achieve the primary objective of establishing a communication setup at a bandwidth of 2.5 GHz for testing Ultra Wideband (UWB) antennas. This was achieved with the aid of commercially available optical system which was modified for the purpose. Beginning with the generation of baseband narrow pulses with energy spanning over a broad frequency range, through multiplexing of different parallel channels carrying these pulses into a single stream, to finally capturing the received signal to understand the effect of the communication link formed; all provided basis for identifying the issues and possible solutions to establishing a reliable communication link at UWB frequency

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

Multilevel inverter switching controller using a field programmable gate array (FPGA)

This paper presents the design and development of a switching controller using a field programmable gate array (FPGA)for a multilevel inverter application. SHE with PSO switching strategy was chosen and pre-calculated offline to obtain optimized switching angles for the power switches in the 5-level transistor-clamped H-bridge (TCHB) multilevel inverter. The designed switching controller produced 5-bit control signals, which connected to the power switches of the 5-level TCHB multilevel inverter. The switching controller utilized less than 1% of the total FPGA logic elements (LEs), which was equivalent to 96 out of 114,480 LEs. The execution speed of the switching controller using the FPGA chip was found to be 99.9% faster than microcontroller (PIC16F877A). Conducted simulation and measurement results verified and validated the switching controller design functionality and requirement.Keywords: multilevel inverter, switching controller; FPGA, general purpose processor(GPP);digital signal processing (DSP); IGBT; Verilog, power consumption;harmonic elimination (SHE).

Software-Defined Radio Demonstrators: An Example and Future Trends

Software-defined radio requires the combination of software-based signal processing and the enabling hardware components. In this paper, we present an overview of the criteria for such platforms and the current state of development and future trends in this area. This paper will also provide details of a high-performance flexible radio platform called the maynooth adaptable radio system (MARS) that was developed to explore the use of software-defined radio concepts in the provision of infrastructure elements in a telecommunications application, such as mobile phone basestations or multimedia broadcasters