Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design

Design of a Low Offset, Low Noise Amplifier for Neural Recording Applications

418-423The design of a capacitive feedback based neural recording amplifier is presented. The prime design requirements in case of neural amplifiers includes low noise, high gain, high CMRR, low power, low area and low offset voltage. However, there is an inherent trade-off between noise-power and area-offset in the design process which needs to be addressed. A Recycling Folded Cascode based Operational Transconductance Amplifier (RFC-OTA) topology is employed to realize the amplifier as it offers better gain and offset voltage as compared to other topologies. The sizing of the transistors has been done with the primary objective of low random offset voltage while meeting other design criteria within the specified range subject to all inherent trade-offs. Simulations have been done in Cadence Virtuoso using SCL 180 nm technology and comparative analysis with other reported designs reveals that the proposed RFC-OTA based neural amplifier design achieves a low random offset voltage of 1.4 mV with a low input noise of 1.38 µV as compared to most of the reported design

Design of Inverter Based CMOS Amplifiers in Deep Nanoscale Technologies

In this work, it is proposed a fully differential ring amplifier topology with a deadzone voltage created by a CMOS resistor with a biasing circuit to increase the robustness over PVT variations. The study focuses on analyzing the performance of the ring amplifier over process, temperature, and supply voltage variations, in order to guarantee a viable industrial employment in a 7 nm FinFET CMOS technology node for being used as residue amplifier in ADCs. A ring amplifier is a small modular amplifier, derived from a ring oscillator. It is simple enough that it can quickly be designed using only a few inverters, capacitors, and switches. It can amplify with rail-to-rail output swing, competently charge large capacitive loads using slew-based charging, and scale well in performance according to process trends. In typical process corner, a gain of 72 dB is achieved with a settling time of 150 ps. Throughout the study, the proposed topology is compared with others presented in literature showing better results over corners and presenting a faster response. The proposed topology isn’t yet suitable for industry use, because it presents one corner significantly slower than the rest, namely process corner FF 125 °C, and process corner FS -40 °C with a small oscillation throughout the entire amplification period. Nevertheless, it proved itself to be a promising technique, showing a high gain and a fast settling without oscillation phase, with room for improvement.Neste trabalho, é proposta uma topologia de ring amplifier com a deadzone a ser criada através de uma resistência CMOS com um circuito de polarização para aumentar a robustez para as variações PVT. O estudo foca-se em analisar a performance do ring amplifier nas variações de processo, temperatura e tensão de alimentação, de forma a garantir um uso viável em indústria na tecnologia de 7 nm FinFET CMOS, para ser usado como amplificador de resíduo em ADCs. Um ring amplifier é um pequeno amplificador modular, derivado do ring oscillator. É simples o suficiente para ser facilmente projetado usando apenas poucos inversores, condensadores e interruptores. Consegue amplificar com rail-to-rail output swing, carregar grandes cargas capacitivas com carregamento slew-based e escalar bem em termos de performance de acordo com o processo. No typical process corner, foi obtido um ganho de 72 dB com um tempo de estabilização de 150 ps. Durante o estudo, a topologia proposta é comparada com outras presentes na literatura mostrando melhores resultados over corners e apresentando uma resposta mais rápida. A topologia proposta ainda não está preparada para uso industrial uma vez que apresenta um corner significativamente mais lento que os restantes, nomeadamente, process corner FF 125 °C, e outro process corner, FS -40 °C, com uma pequena oscilação durante todo o período de amplificação. Todavia, provou ser uma técnica promissora, apresentando um ganho elevado e uma rápida estabilização sem fase de oscilação, com espaço para melhoria

Design of Touch Screen Controller IC for Transparent Fingerprint Sensor

Department of Electrical EngineeringA design of system architecture and analog-front-end (AFE) with high SNR and high frame rate for mutual capacitive touch screen with multiple electrodes is presented. Firstly, a differential continuous-mode parallel operation architecture (DCPA) is proposed for large-sized TSP. The proposed architecture achieves a high product of signal-to-noise ratio (SNR) and frame rate, which is a requirement of ROIC for large-sized TSP. DCPA is accomplished by using the proposed differential sensing method with a parallel architecture in a continuous-mode. A continuous-type differential charge amplifier removes the common-mode noise component, and reduces the self-noise by the band-pass filtering effect of the continuous-mode charge amplifier. In addition, the differential parallel architecture cancels the timing skew problem caused by the continuous-mode parallel operation and effectively enhances the power spectrum density of the signal. The proposed ROIC was fabricated using a 0.18-um CMOS process and occupied an active area of 1.25 mm2. The proposed system achieved a 72 dB SNR and 240 Hz frame rate with a 32 channel TX by 10 channel RX mutual capacitive TSP. Moreover, the proposed differential-parallel architecture demonstrated higher immunity to lamp noise and display noise. The proposed system consumed 42.5 mW with a 3.3-V supply. Secondly, readout IC (ROIC) with a differential coded multiple signaling method (DCMS) is proposed to detect an atto-farad capacitance difference for fingerprint recognition in fingerprint TSP. A readout IC with high SNR and fast frame rate are required in the fingerprint recognition. However, the capacitance difference by the ridge and valley of the fingerprint is very small, so that the signal-to-noise ratio is very low. In addition, it takes long time to scan whole fingerprint TSP with multiple electrodes. A fully differential architecture with differential signaling is proposed to detect the low capacitance difference in fingerprint TSP. The internal noise generated is minimized by 2nd fully differential operational amplifier and external noise is eliminated by a lock-in sensing structure. In addition, DCMS reduces an AC offset and enhances a higher product of SNR and frame rate in multiple channels. The proposed architectures can distinguish a 50-atto-farad which is a capacitance difference resulted from the ridges and valley of the finger under the 0.3T glass. The total scan time for 42 ?? 42 fingerprint TSP is less than 21 ms and the power consumption is below 20 mW at 3.3 V supply voltage. IC has been fabricated using a 0.18 ??m standard CMOS process.ope

Low-Power Integrated Circuits For Biomedical Applications

With thousands new cases of spinal cord injury reported everyday, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs, such a state severely deteriorates the patients' quality of life and may even lead to additional medical conditions. Therefore, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient's brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts, having high spatial resolution and signal to noise ratio, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted. To implement a fully implantable system, low-power and miniaturized electronics are needed to reduced heat generation, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system's components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system, namely, ultra low-power brain signal acquisition front-ends, a low-power and inductorless MedRadio transceiver, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillator generates the reference signal for other system's components such as analog to digital converter. Novel techniques to improve important performance parameters (power consumption, low noise operation and interference resilience) have been introduced. Electrical, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces