A reconfigurable low-voltage and low-power millimeter-wave dual-band mixer in 65-nm CMOS

ABSTRACT: In this paper, we propose, investigate, and demonstrate a reconfigurable low-voltage and low-power millimeter-wave mixer in a 65-nm CMOS, which can be switched as either a subharmonic mixer (SHM) or a fundamental mixer (FM) for the dual-band applications. Based on a modified Gilbert mixer topology, the proposed CMOS mixer can operate at a low supply voltage and low local oscillator (LO) pumping power while providing good performance in both SHM and FM modes. To the best of our knowledge, this is the first reported Gilbert SHM based on the stacked switching quads in a low-voltage CMOS technology. Under 1-V supply voltage and -3-dBm LO pumping power, the measured conversion gain (CG) of the proposed CMOS mixer is -4.8 ± 1.5 dB from 34 to 56 GHz and -0.1 ± 1.5 dB from 17 to 43 GHz in the SHM and FM modes, respectively. The measured double-sideband (DSB) noise figure (NF) is 18.5-20 dB from 37 to 49 GHz and 12.4-14 dB from 17 to 35 GHz in the SHM and FM modes, respectively. The measured input third-order intercept point (IIP3) is 2.9 and 3.4 dBm, respectively, for the SHM and FM modes at the LO frequency of 22 GHz. In addition, the total dc power consumption of the proposed mixer including output buffers is 7 mW in both the operation modes

Multifunction Transceiver Architecture and Technology for Future Wireless Systems

RÉSUMÉ Depuis la toute première transmission sans fil, les ondes radiofréquences ont été progressivement mises en valeur et exploitées dans un nombre de plus en plus important d'applications. Parmi toutes ces applications, la détection et la télécommunication sont sans doute les plus indispensables de nos jours. Il existe un grand nombre d’utilisations des radiofréquences, incluant les transports intelligents pour lesquels les véhicules doivent être équipés à la fois de radars et de dispositifs de communication afin d’être capables de détecter l'environnement ainsi que de réaliser la communication avec d'autres unités embarquées. La technologie émergente 5G est un autre exemple pour lequel plusieurs capteurs et radios devraient être capables de coopérer de manière autonome ou semi-autonome. Les principes de fonctionnement des systèmes radars et radio sont toutefois différents. Ces différences fondamentales peuvent entraîner l'utilisation de différentes architectures de traitement du signal et d'émetteur-récepteur, ce qui peut poser des problèmes pour l'intégration de toutes les fonctions requises au sein d'une seule et même plate-forme. En dehors de cela, certaines applications requièrent plusieurs fonctions simultanément dans un même dispositif. Par exemple, les systèmes de détection d'angle d'arrivée 2D nécessitent d'estimer l'angle d'arrivée (AOA) du faisceau entrant dans les plans horizontal et vertical simultanément. La communication radio multi-bandes et multi-modes est un autre exemple pour lequel un système radio doit être capable de communiquer dans plusieurs bandes de fréquences et dans plusieurs modes, par exemple, un duplexage en fonction de la fréquence ou du temps. À première vue, on peut penser que l'assemblage de plusieurs dispositifs distincts n'est pas la meilleure solution en ce qui concerne le coût, la simplicité et la fonctionnalité. Par conséquent, une direction de recherche consiste à proposer une architecture d'émetteur-récepteur unifiée et compacte plutôt qu’une plate-forme assemblant de multiples dispositifs distincts. C’est cette problématique qui est spécifiquement abordée dans ce travail. Selon les fonctions à intégrer dans un seul et unique système multifonctionnel, la solution peut traiter plusieurs aspects simultanément. Par exemple, toute solution réalisant l'intégration de fonctions liées au radar et à la radio devrait traiter deux aspects principaux, à savoir : la forme d'onde opérationnelle et l'architecture frontale RF.----------ABSTRACT Since the very early wireless transmission of radiofrequency signals, it has been gradually flourished and exploited in a wider and wider range of applications. Among all those applications of radio technology, sensing and communicating are undoubtedly the most indispensable ones. There are a large number of practical scenarios such as intelligent transportations in which vehicles must be equipped with both radar and communication devices to be capable of both sensing the environment and communication with other onboard units. The emerging 5G technology can be another important example in which multiple sensors and radios should be capable of cooperating with each other in an autonomous or semi-autonomous manner. The operation principles of these radar and radio devices are different. Such fundamental differences can result in using different operational signal, distinct signal processing, and transceiver architectures in these systems that can raise challenges for integration of all required functions within a single platform. Other than that, there exist some applications where several functions of a single device (i.e. sensor or radio) are required to be executed simultaneously. For example, 2D angle-of-arrival detection systems require estimating the angle of arrival (AOA) of the incoming beam in both horizontal and vertical planes at the same time. Multiband and multimode radio communication is another example of this kind where a radio system is desired to be capable of communication within several frequency bands and in several modes, e.g., time or frequency division duplexing. At a first glance, one can feel that the mechanical assembling of several distinct devices is not the best solution regarding the cost, simplicity and functionality or operability. Hence, the research attempt in developing a rather unified and compact transceiver architecture as opposed to a classical platform with assembled multiple individual devices comes out of horizon, which is addressed specifically in this work. Depending on the wireless functions that are to be integrated within a single multifunction system, the solution should address multiple aspects simultaneously. For instance, any solution for integrating radar and radio related functions should be able to deal with two principal aspects, namely operational waveform and RF front-end architecture. However, in some other above- mentioned examples such as 2D DOA detection system, identical operational waveform may be used and the main challenge of functional integration would pertain to a unification of multiple mono-functional transceivers

Radiofrequency architectures and technologies for software defined radio

Six-port network is an interesting radiofrequency architecture with multiple possibilities. Since it was firstly introduced in the seventies as an alternative network analyzer, the six-port network has been used for many applications, such as homodyne receivers, radar systems, direction of arrival estimation, UWB (Ultra-Wide-Band), or MIMO (Multiple Input Multiple Output) systems. Currently, it is considered as a one of the best candidates to implement a Software Defined Radio (SDR). This thesis comprises an exhaustive study of this promising architecture, where its fundamentals and the state-of-the-art are also included. In addition, the design and development of a SDR 0.3-6 GHz six-port receiver prototype is presented in this thesis, which is implemented in conventional technology. The system is experimentally characterized and validated for RF signal demodulation with good performance. The analysis of the six-port architecture is complemented by a theoretical and experimental comparison with other radiofrequency architectures suitable for SDR. Some novel contributions are introduced in the present thesis. Such novelties are in the direction of the highly topical issues on six-port technique: development and optimization of real-time I-Q regeneration techniques for multiport networks; and search of new techniques and technologies to contribute to the miniaturization of the six-port architecture. In particular, the novel contributions of this thesis can be summarized as: - Introduction of a new real-time auto-calibration method for multiport receivers, particularly suitable for broadband designs and high data rate applications. - Introduction of a new direct baseband I-Q regeneration technique for five-port receivers. - Contribution to the miniaturization of six-port receivers by the use of the multilayer LTCC (Low Temperature Cofired Ceramic) technology. Implementation of a compact (30x30x1.25 mm) broadband (0.3-6 GHz) six-port receiver in LTTC technology. The results and conclusions derived from this thesis have been satisfactory, and quite fruitful in terms of publications. A total of fourteen works have been published, considering international journals and conferences, and national conferences. Aditionally, a paper has been submitted to an internationally recognized journal, which is currently under review

Analog-to-digital interface design in wireless receivers

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications

Ultra Low Power FM-UWB Transceiver for High-Density Wireless Sensor Networks

The WiseSkin project aims to provide a non-invasive solution for restoration of a natural sense of touch to persons using prosthetic limbs. By embedding sensor nodes into the silicone coating of the prosthesis, which acts as a sensory skin, WiseSkin targets to provide improved gripping, manipulation and mobility for amputees. Flexibility, freedom of movement and comfort demand unobtrusive, highly miniaturized, low-power sensing capabilities built into the artificial skin, which is then integrated with a sensory feedback system. Wireless communication between the sensor nodes provides more flexibility, better scalability and robustness compared to wired solution, and is therefore a preferred approach for WiseSkin. Design of an RF transceiver tailored for the specific needs of WiseSkin is the topic of this work. The properties of FM ultra-wide band (FM-UWB) modulation make it a good candidate for High-Density Wireless Sensor Networks (HD-WSN). The proposed FM-UWB receivers take advantage of short range to reduce power consumption, and exploit robustness of this wideband modulation scheme. The LNA, identified as the biggest consumer, is removed and signal is directly converted to dc, where amplification and demodulation are performed. Owing to 500 MHz bandwidth, frequency offset and phase noise can be tolerated, and a low-power, free-running ring oscillator can be used to generate the LO signal. The receiver is referred to as an approximate zero-IF receiver. Two receiver architectures are studied. The first one performs quadrature downconversion, and owing to the demodulator linearity, provides the multi-user capability. In the second receiver, quadrature demodulation is replaced by the single-ended one. Due to the nature of the demodulator, sensitivity degrades, and multiple FM-UWB signals cannot be resolved, but the consumption is almost halved compared to the first receiver. The proposed approach is verified through two integrations, both in a standard 65 nm bulk CMOS process. In the first run, a standalone quadrature receiver was integrated. Power consumption of 423 uW was measured, while achieving -70 dBm sensitivity. Good narrow-band interference rejection and multiuser capability with up to 4 FM-UWB channels could be achieved. In the second run, a full transceiver is integrated, with both quadrature and single-ended receivers and a transmitter, all sharing a single IO pad, without the need for any external passive components or switches. The quadrature receiver, with on-chip baseband processing and multi-user support, in this case consumes 550 uW, with a sesensitivity of -68 dBm. The low power receiver consumes 267 uW, and provides -57 dBm sensitivity, at a single FM-UWB channel. The implemented trantransmitter transmits a 100 kb/s FM-UWB signal at -11.4 dBm, while drawing 583 uW from the 1 V supply. The on-chip clock recovery allows reference frequency offset up to 8000 ppm. Since state of the art on-chip RC oscillators can provide below 2100 ppm across the temperature range of interest, the implemented transceiver demonstrates the feasibility of a fully integrated FM-UWB radio with no need for a quartz reference or any external components. In addition, the transceiver can tolerate up to 3 dBm narrow-band interferer at 2.4 GHz. Such a strong signal can be used to remotely power the sensor nodes inside the artificial skin and enable a truly wirelessWiseSkin solution

DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

Subsampling receivers with applications to software defined radio systems

Este trabajo de tesis propone la utilización sistemas basados en submuestreo como una alternativa para la implementación de la etapa de down-conversion de los receptores de radio frecuencia (RF) empleados para aplicaciones multi-estándar y SDR (Software Defined Radio). El objetivo principal será el de optimizar el diseño en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el número de componentes al mínimo es clave cuando un mismo receptor procesa diferentes estándares de comunicación, las arquitecturas basadas en submuestreo han sido seleccionadas, donde la reusabilidad de los componentes empleados es posible, así como la reducción de los costes totales de los receptores de comunicación y de los equipos de certificación que emplean estas arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topología del receptor. Como la idea de la tecnología SDR es implementar todas las funcionalidades del receptor (filtrado, amplificación) en el dominio digital, el convertidores analógico-digital (ADC) deberá estar localizado en la cadena de recepción lo más cerca posible a la antena, siendo el objetivo final el convertir la señal directamente de RF a digital. Sin embargo, con los actuales ADC no es posible implementar esta idea debido al alto ancho de banda que necesitarían sin perder resolución para cubrir las especificaciones de los estándares de comunicaciones inalámbricas. Por tanto, los sistemas basados en submuestreo se presentan como la opción más adecuada para implementar este tipo de sistemas debido a que pueden muestrear la señal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la elección de la frecuencia de muestreo. De este modo, los requerimientos del ADC serán relajados ya que, usando estas arquitecturas, este componente procesará la señal a frecuencias intermedias. Una vez se han introducido los conceptos principales de las técnicas de submuestreo, esta tesis doctoral presenta el diseño de una tarjeta de adquisición de datos basada en submuestreo con la finalidad de ser implementada como un receptor de test y certificación de banda ancha. El sistema propuesto proporciona una alta resolución para un elevado ancho de banda, a partir del uso de un S&H de bajo jitter y de un convertidor analógico digital ADC que trabaja a frecuencias intermedias. El sistema es implementado usando dispositivos comerciales en una placa de circuito impreso diseñada y fabricada, y cuya caracterización experimental muestra una resolución de más 8 bits para un ancho de banda analógico de 20 MHz. Concretamente, la resolución medida será mayor de 9 bits hasta una frecuencia de entrada de 2.9 GHz y mayor de 8 bits para una frecuencia de entrada de hasta 6.5 GHz, lo cual resulta suficiente para cubrir los requerimientos de la mayor parte de los actuales estándares de comunicaciones inalámbricas (GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX). Sin embargo, los receptores basados en submuestreo presentan algunos importantes inconvenientes, como son adicionales fuentes de ruido (jitter y plegado de ruido térmico) y una dificultad añadida para implementarlo en escenarios multi-banda y no lineales. Acerca del plegado de ruido en la banda de interés, esta tesis propone el uso de una técnica basada en una arquitectura de reloj múltiple con el objetivo de aumentar la resolución y cubrir un número mayor de estándares para su test y certificación. Empleando una frecuencia de muestreo mayor para el caso del S&H, se conseguirá reducir este efecto, aumentando la resolución en aproximadamente 0.5-1 bit respecto al caso de sólo usar una fuente de reloj. Las expresiones teóricas de esta mejora son desarrolladas y presentadas en esta tesis, siendo posteriormente corroboradas de modo experimental. Por otra parte, esta tesis también propone novedosas técnicas para la aplicación de estos sistemas de submuestreo en entornos multi-banda y no lineales, los cuales presentan desafíos adicionales por el hecho de existir la posibilidad de solapamiento entre la señal de interés y los otros canales de comunicación, así como de solapamiento con sus armónicos. De este modo, esta tesis extiende el uso de los sistemas basados en submuestreo para este tipo de entornos, proponiendo técnicas para la elección de la frecuencia óptima de muestreo que evitan el solapamiento entre señales, a la vez que consiguen incrementar la resolución del receptor. Finalmente, se presentará la optimización en cuanto a características de ruido de un receptor concreto para aplicaciones de banda dual en entornos no lineales. Dicho receptor estará basado en las técnicas de reloj múltiple presentadas anteriormente y en una estructura de multi-filtro entre el S&H y el ADC. El sistema diseñado podrá emplearse para diversas aplicaciones a ambos lados de la cadena de comunicación, tal como en receptores de detección de espectro para radio cognitiva, o implementando el bucle de realimentación de un transmisor para la linealización de amplificadores de potencia. Por tanto, la presente tesis doctoral cuenta con tres contribuciones diferenciadas. La primera de ellas es la dedicada al diseño de un prototipo de recepción multi-estándar basado en submuestreo para aplicaciones de test y certificación. La segunda aportación es la dedicada a la optimización de las especificaciones de ruido a partir de las técnicas presentadas basadas en reloj múltiple. Por último, la tercera contribución principal es la relacionada con la extensión de este tipo de técnicas a sistemas multi-banda en entornos no lineales. Todas estas contribuciones han sido estudiadas teóricamente y experimentalmente validadas

Characterization and modelling of software defined radio front-ends

Doutoramento em Engenharia ElectrotécnicaO presente trabalho tem por objectivo estudar a caracterização e modelação de arquitecturas de rádio frequência para aplicações em rádios definidos por software e rádios cognitivos. O constante aparecimento no mercado de novos padrões e tecnologias para comunicações sem fios têm levantado algumas limitações à implementação de transceptores rádio de banda larga. Para além disso, o uso de sistemas reconfiguráveis e adaptáveis baseados no conceito de rádio definido por software e rádio cognitivo assegurará a evolução para a próxima geração de comunicações sem fios. A ideia base desta tese passa por resolver alguns problemas em aberto e propor avanços relevantes, tirando para isso partido das capacidades providenciadas pelos processadores digitais de sinal de forma a melhorar o desempenho global dos sistemas propostos. Inicialmente, serão abordadas várias estratégias para a implementação e projecto de transceptores rádio, concentrando-se sempre na aplicabilidade específica a sistemas de rádio definido por software e rádio cognitivo. Serão também discutidas soluções actuais de instrumentação capaz de caracterizar um dispositivo que opere simultaneamente nos domínios analógico e digital, bem como, os próximos passos nesta área de caracterização e modelação. Além disso, iremos apresentar novos formatos de modelos comportamentais construídos especificamente para a descrição e caracterização não-linear de receptores de amostragem passa-banda, bem como, para sistemas nãolineares que utilizem sinais multi-portadora. Será apresentada uma nova arquitectura suportada na avaliação estatística dos sinais rádio que permite aumentar a gama dinâmica do receptor em situações de multi-portadora. Da mesma forma, será apresentada uma técnica de maximização da largura de banda de recepção baseada na utilização do receptor de amostragem passa-banda no formato complexo. Finalmente, importa referir que todas as arquitecturas propostas serão acompanhadas por uma introdução teórica e simulações, sempre que possível, sendo após isto validadas experimentalmente por protótipos laboratoriais.This work investigates the characterization and modeling of radio frequency front-ends for software defined radio and cognitive radio applications. The emergence of new standards and technologies in the wireless communications market are raising several issues to the implementation of wideband transceiver systems. Also, reconfigurable and adaptable systems based on software defined and cognitive radio models are paving the way for the next generation of wireless systems. In this doctoral thesis the fundamental idea is to address the particular open issues and propose appropriate advancements by exploring and taking profit from new capabilities of digital signal processors in a way to improve the overall performance of the novel schemes. Receiver and transmitter strategies for radio communications are summarized by concentrating on the usability for software defined radio and cognitive radio systems. Available instrumentation and next steps for analog and digital radio frequency hardware characterization is also discussed. Wideband behavioral model formats are proposed for nonlinear description and characterization of bandpass sampling receivers, as well as, for multi-carrier nonlinear systems operation. The proposed models share a great flexibility and have the freedom to be simply expanded to other fields. A new design for receiver dynamic range improvement in multi-carrier scenarios is proposed, which is supported on the useful wireless signals statistical evaluation. Additionally, receiver-side bandwidth maximization based on higher-order bandpass sampling approaches is evaluated. All the proposed designs and modeling strategies are accompanied by theoretical backgrounds and simulations whenever possible, being then experimentally validated by laboratory prototypes

Investigation of high bandwith biodevices for transcutaneous wireless telemetry

PhD ThesisBIODEVICE implants for telemetry are increasingly applied today in various areas applications. There are many examples such as; telemedicine, biotelemetry, health care, treatments for chronic diseases, epilepsy and blindness, all of which are using a wireless infrastructure environment. They use microelectronics technology for diagnostics or monitoring signals such as Electroencephalography or Electromyography. Conceptually the biodevices are defined as one of these technologies combined with transcutaneous wireless implant telemetry (TWIT). A wireless inductive coupling link is a common way for transferring the RF power and data, to communicate between a reader and a battery-less implant. Demand for higher data rate for the acquisition data returned from the body is increasing, and requires an efficient modulator to achieve high transfer rate and low power consumption. In such applications, Quadrature Phase Shift Keying (QPSK) modulation has advantages over other schemes, and double the symbol rate with respect to Binary Phase Shift Keying (BPSK) over the same spectrum band. In contrast to analogue modulators for generating QPSK signals, where the circuit complexity and power dissipation are unsuitable for medical purposes, a digital approach has advantages. Eventually a simple design can be achieved by mixing the hardware and software to minimize size and power consumption for implantable telemetry applications. This work proposes a new approach to digital modulator techniques, applied to transcutaneous implantable telemetry applications; inherently increasing the data rate and simplifying the hardware design. A novel design for a QPSK VHDL modulator to convey a high data rate is demonstrated. Essentially, CPLD/FPGA technology is used to generate hardware from VHDL code, and implement the device which performs the modulation. This improves the data transmission rate between the reader and biodevice. This type of modulator provides digital synthesis and the flexibility to reconfigure and upgrade with the two most often languages used being VHDL and Verilog (IEEE Standard) being used as hardware structure description languages. The second objective of this thesis is to improve the wireless coupling power (WCP). An efficient power amplifier was developed and a new algorithm developed for auto-power control design at the reader unit, which monitors the implant device and keeps the device working within the safety regulation power limits (SAR). The proposed system design has also been modeled and simulated with MATLAB/Simulink to validate the modulator and examine the performance of the proposed modulator in relation to its specifications.Higher Education Ministry in Liby