5,530 research outputs found
Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies
Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC
allows various small and large electronic systems to be implemented in a single chip. This
approach enables the miniaturization of design blocks that leads to high density transistor
integration, faster response time, and lower fabrication costs. To reap the benefits of SOC
and uphold the miniaturization of transistors, innovative power delivery and power
dissipation management schemes are paramount. This dissertation focuses on on-chip
integration of power delivery systems and managing power dissipation to increase the
lifetime of energy storage elements. We explore this problem from two different angels:
On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce
parasitic effects, and allow faster and efficient power delivery for microprocessors. Power
gating techniques, on the other hand, reduce the power loss incurred by circuit blocks
during standby mode.
Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide
semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic
dependency on the dynamic switching power and a more than linear dependency on static
power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power
loss, the supply power should be reduced. A significant reduction in power dissipation
occurs when portions of a microprocessor operate at a lower voltage level. This reduction
in supply voltage is achieved via voltage regulators or converters. Voltage regulators are
used to provide a stable power supply to the microprocessor. The conventional off-chip
switching voltage regulator contains a passive floating inductor, which is difficult to be
implemented inside the chip due to excessive power dissipation and parasitic effects.
Additionally, the inductor takes a very large chip area while hampering the scaling process.
These limitations make passive inductor based on-chip regulator design very unattractive
for SOC integration and multi-/many-core environments. To circumvent the challenges,
three alternative techniques based on active circuit elements to replace the passive LC filter
of the buck convertor are developed. The first inductorless on-chip switching voltage
regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass
filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse
with modulation (PWM). The second approach is a supplementary design utilizing a hybrid
low drop-out scheme to lower the output ripple of the switching regulator over a wider
frequency range. The third design approach allows the integration of an entire power
management system within a single chipset by combining a highly efficient switching
regulator with an intermittently efficient linear regulator (area efficient), for robust and
highly efficient on-chip regulation.
The static power (Pstatic) or subthreshold leakage power (Pleak) increases with
technology scaling. To mitigate static power dissipation, power gating techniques are
implemented. Power gating is one of the popular methods to manage leakage power during
standby periods in low-power high-speed IC design. It works by using transistor based
switches to shut down part of the circuit block and put them in the idle mode. The efficiency
of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A
conventional sleep transistor circuit design requires an additional header, footer, or both
switches to turn off the logic block. This additional transistor causes signal delay and
increases the chip area. We propose two innovative designs for next generation sleep
transistor designs. For an above threshold operation, we present a sleep transistor design
based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit
operation, we implement a sleep transistor utilizing the newly developed silicon-on
ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability
to control the threshold voltage via bias voltage at the back gate makes both devices more
flexible for sleep transistors design than a bulk MOSFET. The proposed approaches
simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep
transistor, and improve power dissipation. In addition, the design provides a dynamically
controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio
Capacitorless DC–DC regulator as a candidate topology for photovoltaic solar facilities
Postprint (published version
Linear-assisted DC/DC converters with modified current-mode control applied to photovoltaic solar systems
This article shows the proposal of a current-mode one-cycle control for linear-assisted DC/DC converters. Linearassisted DC/DC converters are structures that allow to take advantages of the two classic alternatives in the design of power supply systems: voltage linear regulators (classic NPN topology or LDO –low dropout–) and switching DC/DC converters. The current-mode one-cycle control technique is proposed in order to obtain the duty cycle of the linear-assisted converter switch. The proposed structure can provide an output with suitable load and line regulations. Thus, the paper shows the design and simulation results of the proposed current-mode one-cycle linear-assisted converter.Postprint (published version
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Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications
Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped with the ability to sense, compute, communicate with each other and perform tasks in a coordinated manner, security and power management are among the most critical challenges.
Physically unclonable function (PUF) emerges as an important security primitive in hardware-security applications; it provides an object-specific physical identifier hidden within the intrinsic device variations, which is hard to expose and reproduce by adversaries. Yet, designing a compact PUF robust to noise, temperature and voltage remains a challenge.
This thesis presents a novel PUF design approach based on a pair of ultra-compact analog circuits whose output is proportional to absolute temperature. The proposed approach is demonstrated through two works: (1) an ultra-compact and robust PUF based on voltage-compensated proportional-to-absolute-temperature voltage generators that occupies 8.3× less area than the previous work with the similar robustness and twice the robustness of the previously most compact PUF design and (2) a technique to transform a 6T-SRAM array into a robust analog PUF with minimal overhead. In this work, similar circuit topology is used to transform a preexisting on-chip SRAM into a PUF, which further reduces the area in (1) with no robustness penalty.
In this thesis, we also explore techniques for power management circuit design.
Energy harvesting is an essential functionality in an IoT sensor node, where battery replacement is cost-prohibitive or impractical. Yet, existing energy-harvesting power management units (EH PMU) suffer from efficiency loss in the two-step voltage conversion: harvester-to-battery and battery-to-load. We propose an EH PMU architecture with hybrid energy storage, where a capacitor is introduced in addition to the battery to serve as an intermediate energy buffer to minimize the battery involvement in the system energy flow. Test-case measurements show as much as a 2.2× improvement in the end-to-end energy efficiency.
In contrast, with the drastically reduced power consumption of IoT nodes that operates in the sub-threshold regime, adaptive dynamic voltage scaling (DVS) for supply-voltage margin removal, fully on-chip integration and high power conversion efficiency (PCE) are required in PMU designs. We present a PMU–load co-design based on a fully integrated switched-capacitor DC-DC converter (SC-DC) and hybrid error/replica-based regulation for a fully digital PMU control. The PMU is integrated with a neural spike processor (NSP) that achieves a record-low power consumption of 0.61 µW for 96 channels. A tunable replica circuit is added to assist the error regulation and prevent loss of regulation. With automatic energy-robustness co-optimization, the PMU can set the SC-DC’s optimal conversion ratio and switching frequency. The PMU achieves a PCE of 77.7% (72.2%) at VIN = 0.6 V (1 V) and at the NSP’s margin-free operating point
FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation
A new internally compensated low drop-out voltage
regulator based on the cascoded flipped voltage follower is
presented in this paper. Adaptive biasing current and fast
charging/discharging paths have been added to rapidly
charge and discharge the parasitic capacitance of the pass
transistor gate, thus improving the transient response. The
proposed regulator was designed with standard 65-nm
CMOS technology. Measurements show load and line
regulations of 433.80 μV/mA and 5.61 mV/V, respectively.
Furthermore, the output voltage spikes are kept under
76 mV for 0.1 mA to 100 mA load variations and 0.9 V to
1.2 V line variations with rise and fall times of 1 μs. The
total current consumption is 17.88 μA (for a 0.9 V supply
voltage).Ministerio de EconomÃa y Competitividad TEC2015-71072-C3-3-RConsejerÃa de EconomÃa, Innovación y Ciencia. Junta de AndalucÃa P12-TIC-186
Efficient LDO-Assisted DC/DC buck converter for integrated power management system
DC-DC Switching Converters; Voltage Linear Regulators; Linear-Assisted DC-DC Voltage Regulators.Postprint (published version
Synthesizable delay line architectures for digitally controlled voltage regulators
Voltage regulators used in the integrated circuit (IC) industry require precise voltage regulation. In digitally controlled switching converters, this precise voltage regulation is achieved by high resolution digital pulse width modulators (DPWM). Digital delay lines can be used to generate the pulse width modulation (PWM) signal. Conventional delay lines are designed in a full custom design methodology which is extremely slow and expensive compared to register-transfer level (RTL) based designs; also RTL based designs are technology independent so the same design can be used with new technologies. The purpose of this work is to introduce a new architecture for the fully synthesizable digital delay line used in digitally controlled voltage regulators. A comparison between the proposed scheme and the conventional delay line is done post synthesis on the key delay line specifications like linearity, area, complexity, and compensation for process, voltage, and temperature (PVT) variations for multiple clock frequencies. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32nm technology. The comparison showed that the proposed architecture has better linearity, area, and also it has a fast calibration time with respect to conventional delay lines. The delay lines are designed in parameterized way in order to make the design suitable for multiple frequencies
A survey of emerging architectural techniques for improving cache energy consumption
The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students
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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Recent technological advances have greatly improved the performance and
features of embedded systems. With the number of just mobile devices now
reaching nearly equal to the population of earth, embedded systems have truly
become ubiquitous. These trends, however, have also made the task of managing
their power consumption extremely challenging. In recent years, several
techniques have been proposed to address this issue. In this paper, we survey
the techniques for managing power consumption of embedded systems. We discuss
the need of power management and provide a classification of the techniques on
several important parameters to highlight their similarities and differences.
This paper is intended to help the researchers and application-developers in
gaining insights into the working of power management techniques and designing
even more efficient high-performance embedded systems of tomorrow
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