Named Data Networking in Vehicular Ad hoc Networks: State-of-the-Art and Challenges

International audienceInformation-Centric Networking (ICN) has been proposed as one of the future Internet architectures. It is poised to address the challenges faced by today's Internet that include, but not limited to, scalability, addressing, security, and privacy. Furthermore, it also aims at meeting the requirements for new emerging Internet applications. To realize ICN, Named Data Networking (NDN) is one of the recent implementations of ICN that provides a suitable communication approach due to its clean slate design and simple communication model. There are a plethora of applications realized through ICN in different domains where data is the focal point of communication. One such domain is Intelligent Transportation System (ITS) realized through Vehicular Ad hoc NETwork (VANET) where vehicles exchange information and content with each other and with the infrastructure. To date, excellent research results have been yielded in the VANET domain aiming at safe, reliable, and infotainment-rich driving experience. However, due to the dynamic topologies, host-centric model, and ephemeral nature of vehicular communication, various challenges are faced by VANET that hinder the realization of successful vehicular networks and adversely affect the data dissemination, content delivery, and user experiences. To fill these gaps, NDN has been extensively used as underlying communication paradigm for VANET. Inspired by the extensive research results in NDN-based VANET, in this paper, we provide a detailed and systematic review of NDN-driven VANET. More precisely, we investigate the role of NDN in VANET and discuss the feasibility of NDN architecture in VANET environment. Subsequently, we cover in detail, NDN-based naming, routing and forwarding, caching, mobility, and security mechanism for VANET. Furthermore, we discuss the existing standards, solutions, and simulation tools used in NDN-based VANET. Finally, we also identify open challenges and issues faced by NDN-driven VANET and highlight future research directions that should be addressed by the research community

Cooperative Caching in Vehicular Networks - Distributed Cache Invalidation Using Information Freshness

Recent advances in vehicular communications has led to significant opportunities to deploy variety of applications and services improving road safety and traffic efficiency to road users. In regard to traffic management services in distributed vehicular networks, this thesis work evaluates managing storage at vehicles efficiently as cache for moderate cellular transmission costs while still achieving correct routing decision. Road status information was disseminated to oncoming traffic in the form of cellular notifications using a reporting mechanism. High transmission costs due to redundant notifications published by all vehicles following a basic reporting mechanism: Default-approach was overcome by implementing caching at every vehicle. A cooperative based reporting mechanism utilizing cache: Cooperative-approach, was proposed to notify road status while avoiding redundant notifications. In order to account those significantly relevant vehicles for decision-making process which did not actually publish, correspondingly virtual cache entries were implemented. To incorporate the real-world scenario of varying vehicular rate observed on any road, virtual cache entries based on varying vehicular rate was modeled as Adaptive Cache Management mechanism. The combinations of proposed mechanisms were evaluated for cellular transmission costs and accuracy achieved for making correct routing decision. Simulation case studies comprising varying vehicular densities and different false detection rates were conducted to demonstrate the performance of these mechanisms. Additionally, the proposed mechanisms were evaluated in different decision-making algorithms for both information freshness in changing road conditions and for robustness despite false detections. The simulation results demonstrated that the combination of proposed mechanisms was capable of achieving realistic information accuracy enough to make correct routing decision despite false readings while keeping network costs significantly low. Furthermore, using QoI-based decision algorithm in high density vehicular networks, fast adaptability to frequently changing road conditions as well as quick recovery from false notifications by invalidating them with correct notifications were indicated

Efficient Traffic Management Algorithms for the Core Network using Device-to-Device Communication and Edge Caching

Exponentially growing number of communicating devices and the need for faster, more reliable and secure communication are becoming major challenges for current mobile communication architecture. More number of connected devices means more bandwidth and a need for higher Quality of Service (QoS) requirements, which bring new challenges in terms of resource and traffic management. Traffic offload to the edge has been introduced to tackle this demand-explosion that let the core network offload some of the contents to the edge to reduce the traffic congestion. Device-to-Device (D2D) communication and edge caching, has been proposed as promising solutions for offloading data. D2D communication refers to the communication infrastructure where the users in proximity communicate with each other directly. D2D communication improves overall spectral efficiency, however, it introduces additional interference in the system. To enable D2D communication, efficient resource allocation must be introduced in order to minimize the interference in the system and this benefits the system in terms of bandwidth efficiency. In the first part of this thesis, low complexity resource allocation algorithm using stable matching is proposed to optimally assign appropriate uplink resources to the devices in order to minimize interference among D2D and cellular users. Edge caching has recently been introduced as a modification of the caching scheme in the core network, which enables a cellular Base Station (BS) to keep copies of the contents in order to better serve users and enhance Quality of Experience (QoE). However, enabling BSs to cache data on the edge of the network brings new challenges especially on deciding on which and how the contents should be cached. Since users in the same cell may share similar content-needs, we can exploit this temporal-spatial correlation in the favor of caching system which is referred to local content popularity. Content popularity is the most important factor in the caching scheme which helps the BSs to cache appropriate data in order to serve the users more efficiently. In the edge caching scheme, the BS does not know the users request-pattern in advance. To overcome this bottleneck, a content popularity prediction using Markov Decision Process (MDP) is proposed in the second part of this thesis to let the BS know which data should be cached in each time-slot. By using the proposed scheme, core network access request can be significantly reduced and it works better than caching based on historical data in both stable and unstable content popularity

CACHE MANAGEMENT ALGORITHMS: SINGLE AND NETWORKED CACHES

Ph.DDOCTOR OF PHILOSOPH

POWER AND PERFORMANCE STUDIES OF THE EXPLICIT MULTI-THREADING (XMT) ARCHITECTURE

Power and thermal constraints gained critical importance in the design of microprocessors over the past decade. Chipmakers failed to keep power at bay while sustaining the performance growth of serial computers at the rate expected by consumers. As an alternative, they turned to fitting an increasing number of simpler cores on a single die. While this is a step forward for relaxing the constraints, the issue of power is far from resolved and it is joined by new challenges which we explain next. As we move into the era of many-cores, processors consisting of 100s, even 1000s of cores, single-task parallelism is the natural path for building faster general-purpose computers. Alas, the introduction of parallelism to the mainstream general-purpose domain brings another long elusive problem to focus: ease of parallel programming. The result is the dual challenge where power efficiency and ease-of-programming are vital for the prevalence of up and coming many-core architectures. The observations above led to the lead goal of this dissertation: a first order validation of the claim that even under power/thermal constraints, ease-of-programming and competitive performance need not be conflicting objectives for a massively-parallel general-purpose processor. As our platform, we choose the eXplicit Multi-Threading (XMT) many-core architecture for fine grained parallel programs developed at the University of Maryland. We hope that our findings will be a trailblazer for future commercial products. XMT scales up to thousand or more lightweight cores and aims at improving single task execution time while making the task for the programmer as easy as possible. Performance advantages and ease-of-programming of XMT have been shown in a number of publications, including a study that we present in this dissertation. Feasibility of the hardware concept has been exhibited via FPGA and ASIC (per our partial involvement) prototypes. Our contributions target the study of power and thermal envelopes of an envisioned 1024-core XMT chip (XMT1024) under programs that exist in popular parallel benchmark suites. First, we compare XMT against an area and power equivalent commercial high-end many-core GPU. We demonstrate that XMT can provide an average speedup of 8.8x in irregular parallel programs that are common and important in general purpose computing. Even under the worst-case power estimation assumptions for XMT, average speedup is only reduced by half. We further this study by experimentally evaluating the performance advantages of Dynamic Thermal Management (DTM), when applied to XMT1024. DTM techniques are frequently used in current single and multi-core processors, however until now their effects on single-tasked many-cores have not been examined in detail. It is our purpose to explore how existing techniques can be tailored for XMT to improve performance. Performance improvements up to 46% over a generic global management technique has been demonstrated. The insights we provide can guide designers of other similar many-core architectures. A significant infrastructure contribution of this dissertation is a highly configurable cycle-accurate simulator, XMTSim. To our knowledge, XMTSim is currently the only publicly-available shared-memory many-core simulator with extensive capabilities for estimating power and temperature, as well as evaluating dynamic power and thermal management algorithms. As a major component of the XMT programming toolchain, it is not only used as the infrastructure in this work but also contributed to other publications and dissertations