Indirect contact probing method for characterizing vertical interconnects

Department of Electrical EngineeringRecently, vertical interconnects in wafer-level are used to achieve system integration with stacked chips. Although the wafer-level vertical interconnects provide smaller interconnection delay and lower power consumption, popularizing the technology is difficult due to testing issues. A main difficulty in testing vertical interconnects comes from that possible damages caused by the direct-contact probing. Therefore, an indirect contact probing method is presented for safe characterization in waver level. The proposed method is based on the capacitive coupling method. Utilizing a dielectric contactor, the sensitivity of capacitive coupling can be improved with ensuring the protection of vertical interconnects. In addition, extra probe control module and sensor electronics are not required since the dielectric contactor maintains the constant gap. The proposed method is verified in both cases of a single-pair via and multiple vias. The procedure of the proposed method for a single-pair vias starts with one-port calibration. To apply one-port calibration, we have measurements on three different calibration vias by the indirect and the direct-contact probing. From the measurement data, the characteristic of dielectric contactor is fully characterized. After the dielectric contactor is mounted on the DUT containing vertical interconnects, the DUT is measured by the indirect-contact probing manner. Finally, de-embedding the dielectric contactor portion, we can obtain the characteristic of a single-pair via. The proposed method is verified in printed circuit board (PCB) level. The extracted via impedances show a good agreement with the direct-contact probing in frequency ranges 0.8 GHz to 30 GHz and 2.5 GHz to 18 GHz by simulations and measurements, respectively. In the case of multi-via testing, the procedure is similar to a single-pair via extraction but additional fixtures are required. By adopting the socket and calibration substrates, the dielectric contactor consisting of multiple pads can be characterized. From dielectric contactor characteristics corresponding to each via, multiple vias can be extracted based on the reference plane. The extracted impedances of multiple vias show a good agreement with the direct-contact probing up to 24 GHz by simulations and 22 GHz by measurements. From the extracted impedances, we can diagnose all defects among multiple vias. Since the proposed method for multi-via test is limited to testing, the indirect contact probing method for the multi-port characterization is also proposed. It characterizes a multi-port network of a DUT by de-embedding the multi-port characteristics of the dielectric contactor, hence we can also capture inter-via couplings from a multi-port network. Based on simulations, a two-port network is successfully characterized in the range of 0.8 GHz to 24 GHz.ope

Isolationszuverlässigkeit und Lebensdauermodellierung für die Gehäusekonstruktion von Halbleitersensoren

Die vorliegende Arbeit befasst sich mit der Isolationszuverlässigkeit und Lebensdauermodellierung für die Gehäusekonstruktion von Halbleitersensoren. Bei den untersuchten Gehäusekonstruktionen handelt es sich insbesondere um Stromsensoren, die auf der Messung des Magnetfeldes eines stromdurchflossenen Leiters basieren. Dabei werden spannungsinduzierte Fehlermechanismen und ihre Auswirkung innerhalb des Sensors diskutiert und ein Lebensdauermodell für den Sensor beschrieben, das auf dem Fehlermechanismus der anodischen Oxidation basiert.:1 THEORETISCHE GRUNDLAGEN DER SENSORKONSTRUKTION 1.1 Grundlagen der Isolationskoordination 1.2 Grundlagen der Sensorkonzeption 1.3 Stand der Technik 1.4 Aufgaben für die Gehäuseentwicklung 2 SPANNUNGSINDUZIERTE FEHLERMECHANISMEN 2.1 Teilentladung 2.2 Dielektrischer Durchbruch 2.3 Chemische Umsetzung von Si 2.4 Migrationsmechanismen 2.5 Leckstrom 3 LEBENSDAUERMODELLIERUNG 3.1 Beschleunigte Alterung 3.2 Modellfunktion für die Lebensdauer 3.3 Lebensdauerkalkulatione

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Evaluating Techniques for Wireless Interconnected 3D Processor Arrays

In this thesis the viability of a wireless interconnect network for a highly parallel computer is investigated. The main theme of this thesis is to project the performance of a wireless network used to connect the processors in a parallel machine of such design. This thesis is going to investigate new design opportunities a wireless interconnect network can offer for parallel computing. A simulation environment is designed and implemented to carry out the tests. The results have shown that if the available radio spectrum is shared effectively between building blocks of the parallel machine, there are substantial chances to achieve high processor utilisation. The results show that some factors play a major role in the performance of such a machine. The size of the machine, the size of the problem and the communication and computation capabilities of each element of the machine are among those factors. The results show these factors set a limit on the number of nodes engaged in some classes of tasks. They have shown promising potential for further expansion and evolution of our idea to new architectural opportunities, which is discussed by the end of this thesis. To build a real machine of this type the architects would need to solve a number of challenging problems including heat dissipation, delivering electric power and Chip/board design; however, these issues are not part of this thesis and will be tackled in future