909 research outputs found

    Design and Analysis of a Low-Power 8-Bit 500 KS/S SAR ADC for Bio-Medical Implant Devices

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    This thesis project involves the design and analysis of an 8-bit Successive Approximation Register (SAR) Analog to Digital Convertor (ADC), designed for low- power applications such as bio-medical implants. The sampling rate for this ADC is 500 KS/s. The power consumption for the whole SAR ADC system was measured to be 2.1 uW. The novelty of this project is the proposal of an extremely energy efficient comparator architecture. The result is the design of a final ADC with reasonable sampling speed, accuracy and low power consumption. In this project, all the different subsystems have been designed at the transistor level with 45 nm CMOS technology. The logical circuit was designed using Verilog language. It was then synthesized and integrated in the overall system

    CMOS Data Converters for Closed-Loop mmWave Transmitters

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    With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

    Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

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    With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

    Accurate Jitter Decomposition in High-Speed Links

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    In a high-speed digital communication system, jitter performance plays a crucial role in Bit-Error Rate (BER). It is important to accurately derive each type of jitter as well as total jitter (TJ) and to identify the root causes of jitter by jitter decomposition. In this work, we propose new jitter decomposition techniques in high-speed links testing. The background of jitter decomposition is described in chapter 1. In chapter 2, duty cycle distortion jitter amplification is introduced. As channel loss results in both ISI and jitter amplification, DCD amplification is a big concern in high-speed links. The derivation of a formula of DCD amplification for data channels is included and the calculation result matches the time-domain simulation in the system. Chapter 3 provides an accurate jitter decomposition algorithm using Least Squares (LS) which simultaneously separates ISI, RJ, and PJ. A new time domain ISI model is proposed, which is faster and more accurate than the conventional ISI model. This algorithm obtains the estimated individual jitter component value with fine accuracy by using less samples of total jitter data compared with conventional methods. The simulation and measurement show the accuracy and efficiency of this algorithm with less data samples. In chapter 4, a low-cost comparator-based jitter decomposition algorithm is proposed. Instead of using TIE jitter sequence to decompose, it uses a low cost and simple comparator network to identify the deviation of current sampling positions from the ideal sampling positions to represent the TIE. It simultaneously separates ISI, DCD, and PJ and can achieve similar accuracy compared to the instrument test. Both the simulation and measurement show the decomposition algorithm with great accuracy and efficiency. In chapter 5, a low cost and simple dithering method to improve the test of linearity of analog-to-digital converter (ADC) is proposed. This method exhibits an improvement and enhancement for the ultra-fast segmented model identification of linearity error (uSMILE) algorithm which reduces 99% of the test time compared to the conventional method. In this study, we proposed three types of distribution dithering methods adding to the ramp input signal to reduce the estimation error when uSMILE was applied in low resolution ADCs. The fix pattern distribution was proved as the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fix-pattern distributions. Both the simulation results and hardware measurement indicate that the estimation error can be significantly reduced in 12-bit SAR ADC with effective dithering

    Variable Precision Tandem Analog-to-Digital Converter (ADC)

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    This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence. As part of the design, the concept of total real-time optimization is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes. The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization. Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components
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