Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

BMSN and SpiderNet as large scale ATM switch interconnection architectures.

by Kin-Yu Cheung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 64-[68]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Multistage Interconnection Architectures --- p.2Chapter 1.2 --- Interconnection Topologies --- p.4Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7Chapter 1.4 --- Organization --- p.8Chapter 1.5 --- Publication --- p.9Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13Chapter 2.1 --- Introduction --- p.13Chapter 2.2 --- Architecture --- p.14Chapter 2.2.1 --- Topology --- p.14Chapter 2.2.2 --- Switch Modules --- p.15Chapter 2.3 --- Routing --- p.17Chapter 2.3.1 --- VP/VC Routing --- p.18Chapter 2.3.2 --- VP/VC Routing Control --- p.22Chapter 2.3.3 --- Cell Routing --- p.23Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24Chapter 2.4 --- SpiderNet --- p.25Chapter 2.5 --- Performance and Discussion --- p.26Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26Chapter 2.5.2 --- Network Capacity --- p.29Chapter 2.6 --- Concluding Remarks --- p.30Chapter 3 --- Multichannel ATM Switching --- p.39Chapter 3.1 --- Introduction --- p.39Chapter 3.2 --- Switch Design --- p.40Chapter 3.3 --- Channel Allocation Algorithms --- p.41Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51Chapter 3.4 --- Performance and Discussion --- p.53Chapter 3.5 --- Concluding Remarks --- p.57Chapter 4 --- Conclusion --- p.62Bibliography --- p.6

Designing a large scale switch interconnection architecture and a study of ATM scheduling algorithms.

by Yee Ka Chi.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 101-[106]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.1.1 --- Large Scale Switch Interconnections --- p.2Chapter 1.1.2 --- Multichannel Switching and Resequencing --- p.6Chapter 1.1.3 --- Scheduling --- p.7Chapter 2 --- Hierarchical Banyan Switch Interconnection --- p.12Chapter 2.1 --- Introduction --- p.12Chapter 2.2 --- Switch Architecture --- p.13Chapter 2.3 --- Switch Operation --- p.19Chapter 2.3.1 --- Call Setup --- p.19Chapter 2.3.2 --- Cell Routing --- p.21Chapter 2.3.3 --- Fault Tolerance --- p.27Chapter 2.4 --- Call Blocking Analysis --- p.28Chapter 2.4.1 --- Dilated Banyan --- p.29Chapter 2.4.2 --- Dilated Benes Network --- p.30Chapter 2.4.3 --- HBSI --- p.30Chapter 2.5 --- Results and Discussions --- p.31Chapter 2.6 --- Summary --- p.37Chapter 3 --- Multichannel Switching and Resequencing --- p.40Chapter 3.1 --- Introduction --- p.40Chapter 3.2 --- Channel Assignment --- p.41Chapter 3.2.1 --- VC-Based Channel Allocation Mechanism --- p.41Chapter 3.2.2 --- Port-Based Channel Allocation Mechanism --- p.45Chapter 3.2.3 --- Trunk-Based Channel Allocation Mechanism --- p.46Chapter 3.3 --- Resequencer --- p.50Chapter 3.3.1 --- Resequencing Algorithm --- p.50Chapter 3.4 --- Results and Discussion --- p.55Chapter 3.5 --- Summary --- p.60Chapter 4 --- Scheduling --- p.62Chapter 4.1 --- Introduction --- p.62Chapter 4.2 --- Virtual Clock Scheduling (VCS) --- p.62Chapter 4.3 --- Gated Virtual Clock Scheduling (GVCS) --- p.70Chapter 4.4 --- Time-Priority Model --- p.75Chapter 4.5 --- Programmable Rate-based Scheduler (PRS) --- p.80Chapter 4.6 --- Integration with Resequencer --- p.83Chapter 4.7 --- Results and Discussions --- p.86Chapter 4.8 --- Summary --- p.96Chapter 5 --- Conclusion --- p.99Bibliography --- p.10

Packet switch architecture for efficient unicast and multicast traffic switching

У дисертацији је предложена једноставна архитектура свича као и алгоритми за ефикасно распоређивање и комутацију уникаст и мултикаст саобраћаја, што је од великог значаја за савремене телекомуникационе мреже у којима количина саобраћаја константно расте. Први дио доприноса ове дисертације чини приједлог рјешења свича за ефикасно управљање уникаст саобраћајем. Ово рјешење је развијено комбинујући најбоље особине постојећих рјешења, при том избјегавајући одређене њихове недостатке. Циљ је да се омогући што брже прослијеђивање пакета уз прихватљив ниво хардверске комплексности. Свич који је развијен у овој дисертацији представља комбинацију свичева са баферима на улазу и свичева који користе Биркхоф-фон Нојман принцип детерминистичког конфигурисања комутационог модула па се не захтијева прорачун конфигурација комутатора. При томе, за разлику од већине рјешења која користе Биркхоф-фон Нојман принцип конфигурисања, у предложеном рјешењу могуће је користити само један физички комутациони модул који би обављао функције оба логичка комутациона модула. Да би се гарантовало да није дошло до поремећаја редослиједа пакета, предложен је и једноставан алгоритам за одабир пакета за слање. Такође, дат је и приједлог унапријеђења подршке за фер сервис првобитно предложеног рјешења за комутацију уникаст саобраћаја. У другом дијелу дисертације, пажња је посвећена унапријеђењу предложеног рјешења за ефикасно управљање и мултикаст саобраћајем. Потреба за овим се јавила као посљедица развоја нових сервиса (нпр. IPTV, онлајн игре итд.) који генеришу такав тип саобраћаја. Како је удио мултикаст саобраћаја у мрежи постао незанемарљив, перформансе свичева који су развијени примарно за уникаст саобраћај значајно опадају. Рјешење које је предложено у првом дијелу дисертације је унапријеђено додавањем модула који служи за управљање мултикаст саобраћајем. Овдје је идеја да се оптерећење са улазног порта који прима мултикаст пакете распореди на више портова који треба да приме те пакете. Овако је на релативно једноставан начин омогућено ефикасно управљање мултикаст саобраћајем. У оквиру дисертације су урађене софтверске симулације које су показале да ова рјешења постижу врло добре перформансе у односу на постојећа. Такође, урађена је и хардверска имплементација предложеног основног уникаст рјешења која је показала релативно скромне захтјеве у погледу хардверских ресурса.The dissertation proposes a simple switch architecture as well as algorithms for efficient scheduling and switching of unicast and multicast traffic, which is of great importance for modern telecommunication networks because their traffic load is constantly and rapidly increasing. The first part of the dissertation’s contributions comprises a proposed switch which efficiently manages unicast traffic. The proposed switch is developed by using the best characteristics of the existing solutions while avoiding some of their drawbacks. The aim is to enable fast packet forwarding while achieving an acceptable level of hardware complexity. The proposed solution combines architecture with buffers at input ports and Birkhoff-von Neumann architecture based on deterministic switch module configurations. Hence, calculation of switch module configurations is not needed. Also, folded architecture is possible, which means that only one physical switching module is used for both switching stages of Birkhoff-von Neumann architecture. A simple algorithm for packet scheduling has been developed in order to avoid packet out-of-sequence problems. Finally, fair service support improvement is introduced for the originally proposed switch solution. The second part of the dissertation is devoted to the enhancement of the proposed unicast switch for efficient management of multicast traffic. The need for multicast support has emerged as a consequence of the development and introduction of new services (such as IPTV, online gaming, etc.) that generate multicast traffic. As the amount of multicast traffic is not negligible anymore, the performance of packet switches that were primarily developed for the unicast traffic is significantly degraded. The solution proposed in the first part of the diseration is enhanced with the module used for multicast traffic management. Here, the idea is that the multicast load at some input port is distributed over ports that are also destination for the multicast packets. This approach enables relatively simple but efficient management of multicast traffic. In this dissertation, software simulations were conducted, which confirmed that proposed solutions achieve very good performances compared to existing solutons. Furthermore, hardware implementation of the proposed basic unicast switch solution shows modest requirements in terms of needed hardware resources

Technology 2000, volume 1

The purpose of the conference was to increase awareness of existing NASA developed technologies that are available for immediate use in the development of new products and processes, and to lay the groundwork for the effective utilization of emerging technologies. There were sessions on the following: Computer technology and software engineering; Human factors engineering and life sciences; Information and data management; Material sciences; Manufacturing and fabrication technology; Power, energy, and control systems; Robotics; Sensors and measurement technology; Artificial intelligence; Environmental technology; Optics and communications; and Superconductivity