Global method for a class of operation optimization problem in steel rolling systems

Many steel products are produced in hot or cold rolling lines with multiple stands. The steel material becomes thinner after being rolled at each stand. Steady-state parameters for controlling the rolling line need to be set so as to satisfy the final product specifications and minimize the total energy consumption. This paper develops a generalized geometric programming model for this setting problem and proposes a global method for solving it. The model can be expressed with a linear objective function and a set of constraints including nonconvex ones. Through constructing lower bounds of some components, the constraints can be converted to convex ones approximately. A sequential approximation method is proposed in a gradually reduced interval to improve accuracy and efficiency. However, the resulting convex programming model in each iteration is still complicated. To reduce the power, it is transformed into a second-order cone programming (SOCP) model and solved using alternating direction method of multipliers (ADMM). The effectiveness of the global method is tested using real data from a hot-rolling line with seven stands. The results demonstrate that the proposed global method solves the problem effectively and reduces the energy consumption

A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation

Abstract — We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved in traditional worst-casing methods by incorporating the effect of spatial correlations in the optimization procedure. The pessimism reduction is achieved by employing a bounded model for the parameter variations, in the form of an uncertainty ellipsoid, which captures the spatial correlation information between the physical parameters. The use of the uncertainty ellipsoid, along with the assumption that the random variables, corresponding to the varying parameters, follow a multivariate Gaussian distribution, enables us to size the circuits for a specified timing yield. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to th

Optimización del diseño de convertidores de potencia CC-CC

L'electrònica ha experimentat una gran evolució durant les últimes dècades. El número de dispositius i aplicacions electrònics ha augmentat exponencialment fins a convertir-se en elements indispensables de la nostra vida quotidiana. Concretament, en el campo de l’electrònica de potencia, els convertidores commutats CC-CC, àmpliament utilitzats en els sistemes d’alimentació d’ equips electrònics, requereixen d’una eficiència elevada. Així, en la tesis es presenta un nou mètode per al disseny de convertidors CC-CC que optimitza una funció objectiu no lineal amb restriccions no lineals. El model desenvolupat aborda, en la majoria dels casos, un problema que consisteix en el disseny òptim de mínimes pèrdues, es a dir, màxima eficiència. A pesar d’això, també es presenta, a mode d’exemple, el disseny òptim de convertidors maximitzant l’ample de banda. Es pretén mostrar així la facilitat amb que pot ser modificat el programa de disseny. El problema ha estat modelat com un programa de Programació Geomètrica per aprofitar les avantatges que ofereix l’optimització convexa.L'electrònica ha experimentat una gran evolució durant les últimes dècades. El número de dispositius i aplicacions electrònics ha augmentat exponencialment fins a convertir-se en elements indispensables de la nostra vida quotidiana. Concretament, en el campo de l’electrònica de potencia, els convertidores commutats CC-CC, àmpliament utilitzats en els sistemes d’alimentació d’ equips electrònics, requereixen d’una eficiència elevada. Així, en la tesis es presenta un nou mètode per al disseny de convertidors CC-CC que optimitza una funció objectiu no lineal amb restriccions no lineals. El model desenvolupat aborda, en la majoria dels casos, un problema que consisteix en el disseny òptim de mínimes pèrdues, es a dir, màxima eficiència. A pesar d’això, també es presenta, a mode d’exemple, el disseny òptim de convertidors maximitzant l’ample de banda. Es pretén mostrar així la facilitat amb que pot ser modificat el programa de disseny. El problema ha estat modelat com un programa de Programació Geomètrica per aprofitar les avantatges que ofereix l’optimització convexa.La electrónica ha experimentado una gran evolución en las últimas décadas. El número de dispositivos y aplicaciones electrónicas ha aumentado exponencialmente hasta convertirse en elementos indispensables en nuestra vida cotidiana. Concretamente, en el campo de la electrónica de potencia, los convertidores conmutados CC-CC, ampliamente utilizados en los sistemas de alimentación de equipos electrónicos, requieren de una eficiencia elevada. Así, en la tesis se presenta un nuevo método para el diseño de convertidores CC-CC que optimiza una función objetivo no lineal con restricciones no lineales. El modelo desarrollado aborda, en la mayoría de los casos, un problema que consiste en el diseño óptimo de mínimas pérdidas, es decir, máxima eficiencia. Sin embargo, también se presenta, a modo de ejemplo, el diseño óptimo de convertidores maximizando el ancho de banda. Se pretende mostrar así la facilidad con que puede ser modificado el programa de diseño. El problema ha sido modelado como un programa de Programación Geométrica para aprovechar las ventajas que ofrece la optimización convexa.The electronics has evolved greatly in recent decades. The number of electronic devices and applications has grown exponentially to become indispensable in our daily lives. Specifically, in the field of power electronics, the power converters DC-DC, widely used in supply systems of electronic equipment, require a high efficiency. Thus, the thesis presents a new method for the design of DC-DC converters to optimize nonlinear objective function with nonlinear constraints. The model developed presented, in most cases, a problem which consists in the optimum design of minimum losses. However, also presents the optimal design of converters maximizing bandwidth. And is intended to show how easy it can be modified the design program. The problem is modelled as a Geometric Programming problem to exploit the advantages of convex optimization

Timing Closure in Chip Design

Achieving timing closure is a major challenge to the physical design of a computer chip. Its task is to find a physical realization fulfilling the speed specifications. In this thesis, we propose new algorithms for the key tasks of performance optimization, namely repeater tree construction; circuit sizing; clock skew scheduling; threshold voltage optimization and plane assignment. Furthermore, a new program flow for timing closure is developed that integrates these algorithms with placement and clocktree construction. For repeater tree construction a new algorithm for computing topologies, which are later filled with repeaters, is presented. To this end, we propose a new delay model for topologies that not only accounts for the path lengths, as existing approaches do, but also for the number of bifurcations on a path, which introduce extra capacitance and thereby delay. In the extreme cases of pure power optimization and pure delay optimization the optimum topologies regarding our delay model are minimum Steiner trees and alphabetic code trees with the shortest possible path lengths. We presented a new, extremely fast algorithm that scales seamlessly between the two opposite objectives. For special cases, we prove the optimality of our algorithm. The efficiency and effectiveness in practice is demonstrated by comprehensive experimental results. The task of circuit sizing is to assign millions of small elementary logic circuits to elements from a discrete set of logically equivalent, predefined physical layouts such that power consumption is minimized and all signal paths are sufficiently fast. In this thesis we develop a fast heuristic approach for global circuit sizing, followed by a local search into a local optimum. Our algorithms use, in contrast to existing approaches, the available discrete layout choices and accurate delay models with slew propagation. The global approach iteratively assigns slew targets to all source pins of the chip and chooses a discrete layout of minimum size preserving the slew targets. In comprehensive experiments on real instances, we demonstrate that the worst path delay is within 7% of its lower bound on average after a few iterations. The subsequent local search reduces this gap to 2% on average. Combining global and local sizing we are able to size more than 5.7 million circuits within 3 hours. For the clock skew scheduling problem we develop the first algorithm with a strongly polynomial running time for the cycle time minimization in the presence of different cycle times and multi-cycle paths. In practice, an iterative local search method is much more efficient. We prove that this iterative method maximizes the worst slack, even when restricting the feasible schedule to certain time intervals. Furthermore, we enhance the iterative local approach to determine a lexicographically optimum slack distribution. The clock skew scheduling problem is then generalized to allow for simultaneous data path optimization. In fact, this is a time-cost tradeoff problem. We developed the first combinatorial algorithm for computing time-cost tradeoff curves in graphs that may contain cycles. Starting from the lowest-cost solution, the algorithm iteratively computes a descent direction by a minimum cost flow computation. The maximum feasible step length is then determined by a minimum ratio cycle computation. This approach can be used in chip design for several optimization tasks, e.g. threshold voltage optimization or plane assignment. Finally, the optimization routines are combined into a timing closure flow. Here, the global placement is alternated with global performance optimization. Netweights are used to penalize the length of critical nets during placement. After the global phase, the performance is improved further by applying more comprehensive optimization routines on the most critical paths. In the end, the clock schedule is optimized and clocktrees are inserted. Computational results of the design flow are obtained on real-world computer chips