Testable Design for Positive Control Flipping Faults in Reversible Circuits

Fast computational power is a major concern in every computing system. The advancement of the fabrication process in the present semiconductor technologies provides to accommodate millions of gates per chip and is also capable of reducing the size of the chips. Concurrently, the complex circuit design always leads to high power dissipation and increases the fault rates. Due to these difficulties, researchers explore the reversible logic circuit as an alternative way to implement the low-power circuit design. It is also widely applied in recent technology trends like quantum computing. Analyzing the correct functional behavior of these circuits is an essential requirement in the testing of the circuit. This paper presents a testable design for the k-CNOT based circuit capable of diagnosing the Positive Control Flipping Faults (PCFFs) in reversible circuits. The proposed work shows that generating a single test vector that applies to the constructed design circuit is sufficient for covering the PCFFs in the reversible circuit. Further, the parity-bit operations are augmented to the constructed testable circuit that produces the parity-test pattern to extract the faulty gate location of PCFFs. Various reversible benchmark circuits are used for evaluating the experimental results to establish the correctness of the proposed fault diagnosis technique. Also a comparative analysis is performed with the existing work

04081 Abstracts Collection -- Theory of Evolutionary Algorithms

From 15.02.04 to 20.02.04, the Dagstuhl Seminar 04081 ``Theory of Evolutionary Algorithms\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

Survey on Quantum Circuit Compilation for Noisy Intermediate-Scale Quantum Computers: Artificial Intelligence to Heuristics

Computationally expensive applications, including machine learning, chemical simulations, and financial modeling, are promising candidates for noisy intermediate scale quantum (NISQ) computers. In these problems, one important challenge is mapping a quantum circuit onto NISQ hardware while satisfying physical constraints of an underlying quantum architecture. Quantum circuit compilation (QCC) aims to generate feasible mappings such that a quantum circuit can be executed in a given hardware platform with acceptable confidence in outcomes. Physical constraints of a NISQ computer change frequently, requiring QCC process to be repeated often. When a circuit cannot directly be executed on a quantum hardware due to its physical limitations, it is necessary to modify the circuit by adding new quantum gates and auxiliary qubits, increasing its space and time complexity. An inefficient QCC may significantly increase error rate and circuit latency for even the simplest algorithms. In this article, we present artificial intelligence (AI)-based and heuristic-based methods recently reported in the literature that attempt to address these QCC challenges. We group them based on underlying techniques that they implement, such as AI algorithms including genetic algorithms, genetic programming, ant colony optimization and AI planning, and heuristics methods employing greedy algorithms, satisfiability problem solvers, dynamic, and graph optimization techniques. We discuss performance of each QCC technique and evaluate its potential limitations

Ternary Max-Min algebra with application to reversible logic synthesis

Ternary reversible circuits are 0.63 times more compact than equivalent binary reversible circuits and are suitable for low-power implementations. Two notable previous works on ternary reversible circuit synthesis are the ternary Galois field sum of products (TGFSOP) expression-based method and the ternary Max-Min algebra-based method. These methods require high quantum cost and large number of ancilla inputs. To address these problems we develop an alternative ternary Max-Min algebra-based method, where ternary logic functions are represented as Max-Min expressions and realized using our proposed multiple-controlled unary gates. We also show realizations of multiple-controlled unary gates using elementary quantum gates. We develop a method for minimization of ternary Max-Min expressions of up to four variables using ternary K-maps. Finally, we develop a hybrid Genetic Algorithm (HGA)-based method for the synthesis of ternary reversible circuits. The HGA has been tested with 24 ternary benchmark functions with up to five variables. On average our method reduces quantum cost by 41.36% and requires 35.72% fewer ancilla inputs than the TGFSOP-based method. Our method also requires 74.39% fewer ancilla inputs than the previous ternary Max-Min algebra-based method

Deep neural networks for quantum circuit mapping

AbstractQuantum computers have become reality thanks to the effort of some majors in developing innovative technologies that enable the usage of quantum effects in computation, so as to pave the way towards the design of efficient quantum algorithms to use in different applications domains, from finance and chemistry to artificial and computational intelligence. However, there are still some technological limitations that do not allow a correct design of quantum algorithms, compromising the achievement of the so-called quantum advantage. Specifically, a major limitation in the design of a quantum algorithm is related to its proper mapping to a specific quantum processor so that the underlying physical constraints are satisfied. This hard problem, known as circuit mapping, is a critical task to face in quantum world, and it needs to be efficiently addressed to allow quantum computers to work correctly and productively. In order to bridge above gap, this paper introduces a very first circuit mapping approach based on deep neural networks, which opens a completely new scenario in which the correct execution of quantum algorithms is supported by classical machine learning techniques. As shown in experimental section, the proposed approach speeds up current state-of-the-art mapping algorithms when used on 5-qubits IBM Q processors, maintaining suitable mapping accuracy