Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System

With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital. As the basic element in the design and analysis phases of digital controllers or filters, a number of unit delays (z-1) have been employed, e.g., in a cascaded structure. Practically, the number of unit delays is designed as an integer, which is related to the sampling frequency as well as the ac signal fundamental frequency (e.g., 50 Hz). More common, the sampling frequency is fixed during operation for simplicity and design. Hence, any disturbance in the ac signal will violate this design rule and it can become a major challenge for digital controllers. To deal with the above issue, this paper first exploits a virtual unit delay (zv-1) to emulate the variable sampling behavior in practical digital signal processors with a fixed sampling rate. This exploitation is demonstrated on a T/4 Delay Phase Locked Loop (PLL) system for a single-phase grid-connected inverter. The T/4 Delay PLL requires to cascade 50 unit delays when implemented (for a 50-Hz system with 10 kHz sampling frequency). Furthermore, digital frequency adaptive comb filters are adopted to enhance the performance of the T/4 Delay PLL when the grid suffers from harmonics. Experimental results have confirmed the effectiveness of the digital filters for advanced control systems

Frequency estimation in DSOGI cells by means of the teager energy operator

Second Order Generalized Integrator (SOGI) cells are used for notch filtering due to their simplicity and their harmonic rejection capability. SOGI and Dual SOGI (DSOGI) filter cells, combined with Frequency Locked Loops (FLL) to adjust the notch frequency, are commonly used in both 1f and 3f grid following (GFL) power converters for synchronization, i.e. SOGI-FLL and DSOGI-FLL, respectively. The FLL relies on a gradient descent method to minimize a cost function built up around one inner SOGI cell variable, e.g., the in-quadrature voltage estimation, and one outer variable, i.e. the error signal due to the SOGI filter cell. As a result, the FLL manages relatively large DC offsets and harmonic distortion passing through the outer SOGI cell variable, which deteriorates the frequency estimation and then, the SOGI-FLL performance. To attenuate such issues, the method proposed in this digest only uses inner SOGI cell variables. It minimizes the deviation between the estimated grid frequency and the frequency of the signal across the SOGI cell, which is detected through the Teager Energy Operator (TEO). The proposal is validated in simulation and experimentally.This work has been supported by the Ministry of Science and Innovation through the project RTI2018-095138-B-C31:"Electrónica de potencia aplicada a la red eléctrica y a procesos industriales": PEGIA

Frequency-Locked Loop Based Estimation of Single-Phase Grid Voltage Parameters

Estimation of amplitude, instantaneous phase, and frequency of a single-phase grid voltage signal are studied in this letter. The proposed approach uses a novel circular limit cycle oscillator (CLO) coupled with a frequency-locked loop. Due to the nonlinear structure of the CLO, the proposed frequency adaptive CLO technique is robust against various perturbations faced in the practical settings, e.g., the discontinuous jump of phase, frequency, and amplitude. The global stability analysis of the CLO and local stability analysis of the frequency adaptive CLO are performed. Experimental results demonstrate the effectiveness of the proposed technique over a very recent technique proposed in the literature