Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Direct sampling receivers for broadband communications

Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices. It is always a dream to design a Software-Defined Radio (SDR) supporting different standards solely based on the software configuration. As integrated-circuit (IC) manufacture and design advance, a partial of SDR can be realized. This thesis investigates one of the most important parts in a SDR: the analog design of a direct sampling (DS) receiver, which mainly consists of a broadband RF front end and a wideband ADC. Especially, a DS receiver shows a great flexibility and efficiency for the simultaneous reception of multiple channels comparing with the traditional parallelism of superheterodyne structure. The research contributions of this work include (1) demonstration and comparative analysis of two new architectures of broadband RFPGAs: voltage-mode: RFPGA-V and current-mode: RFPGA-I. RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range. Besides, with innovative design, no off-chip inductor is needed for the both RFPGAs. (2) The design of a 5-GS/s 10b time-interleaved SAR. The ADC power efficiency is significantly improved by many design techniques: the low-energy CDAC switching scheme, optimized input common-mode voltage for comparator, optimal reduced radix-2 capacitor ratio for low-power reference buffers and higher conversion speed, etc. The lane-to-lane mismatches in a time-interleave ADC are minimized by using optimal floor plan and then are calibrated digitally. Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology.Electrical and Computer Engineerin

Toward Brain Area Sensor Wireless Network

RÉSUMÉ De nouvelles approches d'interfaçage neuronal de haute performance sont requises pour les interfaces cerveau-machine (BMI) actuelles. Cela nécessite des capacités d'enregistrement/stimulation performantes en termes de vitesse, qualité et quantité, c’est à dire une bande passante à fréquence plus élevée, une résolution spatiale, un signal sur bruit et une zone plus large pour l'interface avec le cortex cérébral. Dans ce mémoire, nous parlons de l'idée générale proposant une méthode d'interfaçage neuronal qui, en comparaison avec l'électroencéphalographie (EEG), l'électrocorticographie (ECoG) et les méthodes d'interfaçage intracortical conventionnelles à une seule unité, offre de meilleures caractéristiques pour implémenter des IMC plus performants. Les avantages de la nouvelle approche sont 1) une résolution spatiale plus élevée - en dessous dumillimètre, et une qualité de signal plus élevée - en termes de rapport signal sur bruit et de contenu fréquentiel - comparé aux méthodes EEG et ECoG; 2) un caractère moins invasif que l'ECoG où l'enlèvement du crâne sous une opération d'enregistrement / stimulation est nécessaire; 3) une plus grande faisabilité de la libre circulation du patient à l'étude - par rapport aux deux méthodes EEG et ECoG où de nombreux fils sont connectés au patient en cours d'opération; 4) une utilisation à long terme puisque l'interface implantable est sans fil - par rapport aux deux méthodes EEG et ECoG qui offrent des temps limités de fonctionnement. Nous présentons l'architecture d'un réseau sans fil de microsystèmes implantables, que nous appelons Brain Area Sensor NETwork (Brain-ASNET). Il y a deux défis principaux dans la réalisation du projet Brain-ASNET. 1) la conception et la mise en oeuvre d'un émetteur-récepteur RF de faible consommation compatible avec la puce de capteurs de réseau implantable, et, 2) la conception d'un protocole de réseau de capteurs sans fil (WSN) ad-hoc économe en énergie. Dans ce mémoire, nous présentons un protocole de réseau ad-hoc économe en énergie pour le réseau désiré, ainsi qu'un procédé pour surmonter le problème de la longueur de paquet variable causé par le processus de remplissage de bit dans le protocole HDLC standard. Le protocole adhoc proposé conçu pour Brain-ASNET présente une meilleure efficacité énergétique par rapport aux protocoles standards tels que ZigBee, Bluetooth et Wi-Fi ainsi que des protocoles ad-hoc de pointe. Le protocole a été conçu et testé par MATLAB et Simulink.----------ABSTRACT New high-performance neural interfacing approaches are demanded for today’s Brain-Machine Interfaces (BMI). This requires high-performance recording/stimulation capabilities in terms of speed, quality, and quantity, i.e. higher frequency bandwidth, spatial resolution, signal-to-noise, and wider area to interface with the cerebral cortex. In this thesis, we talk about the general proposed idea of a neural interfacing method which in comparison with Electroencephalography (EEG), Electrocorticography (ECoG), and, conventional Single-Unit Intracortical neural interfacing methods offers better features to implement higher-performance BMIs. The new approach advantages are 1) higher spatial resolution – down to sub-millimeter, and higher signal quality − in terms of signal-to-noise ratio and frequency content − compared to both EEG and ECoG methods. 2) being less invasive than ECoG where skull removal Under recording/stimulation surgery is required. 3) higher feasibility of freely movement of patient under study − compared to both EEG and ECoG methods where lots of wires are connected to the patient under operation. 4) long-term usage as the implantable interface is wireless − compared to both EEG and ECoG methods where it is practical for only a limited time under operation. We present the architecture of a wireless network of implantable microsystems, which we call it Brain Area Sensor NETwork (Brain-ASNET). There are two main challenges in realization of the proposed Brain-ASNET. 1) design and implementation of power-hungry RF transceiver of the implantable network sensors' chip, and, 2) design of an energy-efficient ad-hoc Wireless Sensor Network (WSN) protocol. In this thesis, we introduce an energy-efficient ad-hoc network protocol for the desired network, along with a method to overcome the issue of variable packet length caused by bit stuffing process in standard HDLC protocol. The proposed ad-hoc protocol designed for Brain-ASNET shows better energy-efficiency compared to standard protocols like ZigBee, Bluetooth, and Wi-Fi as well as state-of-the-art ad-hoc protocols. The protocol was designed and tested by MATLAB and Simulink

Low-power adaptive control scheme using switching activity measurement method for reconfigurable analog-to-digital converters

Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

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Department of Electrical EngineeringA Sensor system is advanced along sensor technologies are developed. The performance improvement of sensor system can be expected by using the internet of things (IoT) communication technology and artificial neural network (ANN) for data processing and computation. Sensors or systems exchanged the data through this wireless connectivity, and various systems and applications are possible to implement by utilizing the advanced technologies. And the collected data is computed using by the ANN and the efficiency of system can be also improved. Gas monitoring system is widely need from the daily life to hazardous workplace. Harmful gas can cause a respiratory disease and some gas include cancer-causing component. Even though it may cause dangerous situation due to explosion. There are various kinds of hazardous gas and its characteristics that effect on human body are different each gas. The optimal design of gas monitoring system is necessary due to each gas has different criteria such as the permissible concentration and exposure time. Therefore, in this thesis, conventional sensor system configuration, operation, and limitation are described and gas monitoring system with wireless connectivity and neural network is proposed to improve the overall efficiency. As I already mentioned above, dangerous concentration and permissible exposure time are different depending on gas types. During the gas monitoring, gas concentration is lower than a permissible level in most of case. Thus, the gas monitoring is enough with low resolution for saving the power consumption in this situation. When detecting the gas, the high-resolution is required for the accurate concentration detecting. If the gas type is varied in the above situation, the amount of calculation increases exponentially. Therefore, in the conventional systems, target specifications are decided by the highest requirement in the whole situation, and it occurs increasing the cost and complexity of readout integrated circuit (ROIC) and system. In order to optimize the specification, the ANN and adaptive ROIC are utilized to compute the complex situation and huge data processing. Thus, gas monitoring system with learning-based algorithm is proposed to improve its efficiency. In order to optimize the operation depending on situation, dual-mode ROIC that monitoring mode and precision mode is implemented. If the present gas concentration is decided to safe, monitoring mode is operated with minimal detecting accuracy for saving the power consumption. The precision mode is switched when the high-resolution or hazardous situation are detected. The additional calibration circuits are necessary for the high-resolution implementation, and it has more power consumption and design complexity. A high-resolution Analog-to-digital converter (ADC) is kind of challenges to design with efficiency way. Therefore, in order to reduce the effective resolution of ADC and power consumption, zooming correlated double sampling (CDS) circuit and prediction successive approximation register (SAR) ADC are proposed for performance optimization into precision mode. A Microelectromechanical systems (MEMS) based gas sensor has high-integration and high sensitivity, but the calibration is needed to improve its low selectivity. Conventionally, principle component analysis (PCA) is used to classify the gas types, but this method has lower accuracy in some case and hard to verify in real-time. Alternatively, ANN is powerful algorithm to accurate sensing through collecting the data and training procedure and it can be verified the gas type and concentration in real-time. ROIC was fabricated in complementary metal-oxide-semiconductor (CMOS) 180-nm process and then the efficiency of the system with adaptive ROIC and ANN algorithm was experimentally verified into gas monitoring system prototype. Also, Bluetooth supports wireless connectivity to PC and mobile and pattern recognition and prediction code for SAR ADC is performed in MATLAB. Real-time gas information is monitored by Android-based application in smartphone. The dual-mode operation, optimization of performance and prediction code are adjusted with microcontroller unit (MCU). Monitoring mode is improved by x2.6 of figure-of-merits (FoM) that compared with previous resistive interface.clos

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

NASA Tech Briefs, July 2007

Topics covered include: Miniature Intelligent Sensor Module; "Smart" Sensor Module; Portable Apparatus for Electrochemical Sensing of Ethylene; Increasing Linear Dynamic Range of a CMOS Image Sensor; Flight Qualified Micro Sun Sensor; Norbornene-Based Polymer Electrolytes for Lithium Cells; Making Single-Source Precursors of Ternary Semiconductors; Water-Free Proton-Conducting Membranes for Fuel Cells; Mo/Ti Diffusion Bonding for Making Thermoelectric Devices; Photodetectors on Coronagraph Mask for Pointing Control; High-Energy-Density, Low-Temperature Li/CFx Primary Cells; G4-FETs as Universal and Programmable Logic Gates; Fabrication of Buried Nanochannels From Nanowire Patterns; Diamond Smoothing Tools; Infrared Imaging System for Studying Brain Function; Rarefying Spectra of Whispering-Gallery-Mode Resonators; Large-Area Permanent-Magnet ECR Plasma Source; Slot-Antenna/Permanent-Magnet Device for Generating Plasma; Fiber-Optic Strain Gauge With High Resolution And Update Rate; Broadband Achromatic Telecentric Lens; Temperature-Corrected Model of Turbulence in Hot Jet Flows; Enhanced Elliptic Grid Generation; Automated Knowledge Discovery From Simulators; Electro-Optical Modulator Bias Control Using Bipolar Pulses; Generative Representations for Automated Design of Robots; Mars-Approach Navigation Using In Situ Orbiters; Efficient Optimization of Low-Thrust Spacecraft Trajectories; Cylindrical Asymmetrical Capacitors for Use in Outer Space; Protecting Against Faults in JPL Spacecraft; Algorithm Optimally Allocates Actuation of a Spacecraft; and Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets

Design of Fully-Integrated High-Resolution Radars in CMOS and BiCMOS Technologies

The RADAR, acronym that stands for RAdio Detection And ranging, is a device that uses electromagnetic waves to detect the presence and the distance of an illuminated target. The idea of such a system was presented in the early 1900s to determine the presence of ships. Later on, with the approach of World War II, the radar gained the interest of the army who decided to use it for defense purposes, in order to detect the presence, the distance and the speed of ships, planes and even tanks. Nowadays, the use of similar systems is extended outside the military area. Common applications span from weather surveillance to Earth composition mapping and from flight control to vehicle speed monitoring. Moreover, the introduction of new ultrawideband (UWB) technologies makes it possible to perform radar imaging which can be successfully used in the automotive or medical field. The existence of a plenty of known applications is the reason behind the choice of the topic of this thesis, which is the design of fully-integrated high-resolution radars. The first part of this work gives a brief introduction on high resolution radars and describes its working principle in a mathematical way. Then it gives a comparison between the existing radar types and motivates the choice of an integrated solution instead of a discrete one. The second part concerns the analysis and design of two CMOS high-resolution radar prototypes tailored for the early detection of the breast cancer. This part begins with an explanation of the motivations behind this project. Then it gives a thorough system analysis which indicates the best radar architecture in presence of impairments and dictates all the electrical system specifications. Afterwards, it describes in depth each block of the transceivers with particular emphasis on the local oscillator (LO) generation system which is the most critical block of the designs. Finally, the last section of this part presents the measurement results. In particular, it shows that the designed radar operates over 3 octaves from 2 to 16GHz, has a conversion gain of 36dB, a flicker-noise-corner of 30Hz and a dynamic range of 107dB. These characteristics turn into a resolution of 3mm inside the body, more than enough to detect even the smallest tumor. The third and last part of this thesis focuses on the analysis and design of some important building blocks for phased-array radars, including phase shifter (PHS), true time delay (TTD) and power combiner. This part begins with an exhaustive introduction on phased array systems followed by a detailed description of each proposed lumped-element block. The main features of each block is the very low insertion loss, the wideband characteristic and the low area consumption. Finally, the major effects of circuit parasitics are described followed by simulation and measurement results