Cross-Layer Platform for Dynamic, Energy-Efficient Optical Networks

The design of the next-generation Internet infrastructure is driven by the need to sustain the massive growth in bandwidth demands. Novel, energy-efficient, optical networking technologies and architectures are required to effectively meet the stringent performance requirements with low cost and ultrahigh energy efficiencies. In this thesis, a cross-layer communications platform is proposed to enable greater intelligence and functionality on the physical layer. Providing the optical layer with advanced networking capabilities will facilitate the dynamic management and optimization of optical switching based on performance monitoring measurements and higher-layer attributes. The cross-layer platform aims to create a new framework for networks to incorporate packet-scale measurement subsystems and techniques for monitoring the health of the optical channel. This will allow for quality-of-service- and energy-aware routing schemes, as well as an enhanced awareness of the optical data signals. This thesis first presents the design and development of an optical packet switching fabric. Leveraging a networking test-bed environment to validate networking hypotheses, advanced switching functionalities are demonstrated, including the support for quality-of-service based routing and packet multicasting. The investigated cross-layering is based on emerging optical technologies, enabling packet protection techniques and packet-rate switching fabric reconfiguration. Coupled with fast performance monitoring, the platform will achieve significant performance gains within the endeavor of all-optical switching. Allowing for a more intelligent, programmable optical layer aims to support greater flexibility with respect to bandwidth allocation and potentially a significant reduction in the network's energy consumption. The ultimate deliverable of this work is a high-performance, cross-layer enabled optical network node. The experimental demonstration of an initial prototype creates a dynamic network element with distributed control plane management, featuring fast packet-rate optical switching capabilities and embedded physical-layer performance monitoring modules. The cross-layer box enables an intelligent traffic delivery system that can dynamically manipulate optical switching on a packet-granular scale. With the goal of achieving advanced multi-layer routing and control algorithms, the network node requires an intelligent co-optimization across all the layers. The proposed cross-layer design should drive optical technologies and architectures in an innovative way, in order to fulfill the void between the design of basic photonic devices and the networking protocols that use them. The performance of the entire network -- from the optical components, to the routing algorithms and user applications -- should be optimized in concert. This contribution to the area of cross-layer network design creates an adaptable optical pipe that is extremely flexible and intelligent aware of both the physical optical signals and higher-layer requirements. The impact of this work will be seen in the realization of dynamic, energy-efficient optical communication links in future networking infrastructures

Flexibility for Internet Protocol Backbone Network for Airspace Management Agency Using Dense Wave Division Multiplexing (DWDM)

With the increasing emphasis on service quality in the network of Airspace Management Agencyin the world, coupled with the extensive growth in internet traffic globally it has become a necessity to enhance the backbone network of Airspace Agency with flexibility of Internet Protocol using the Dense Wave Division Multiplexing (DWDM). This is to enhance the backbone network with a resilience of IP-DWDM in case of failure. The IP-DWDM network merges the IP and optical layers making network flexibility possible. The measurement, analysis and evaluations of the backbone network were carried out using simulation method. The throughput, latency and data loss were evaluated and analyzed. The result obtained shows that the Dense Wave Division Multiplexing has relatively high throughput, low latency and less packet drop which resulted in high transmission rate over a long distance and low cost in running the network. The paper therefore, proposes the use of embedded flexibility of the network in achieving an increase in the efficiency and utilization of the bandwidth of the interconnecting core routers of the networks

Architecture design and performance analysis of practical buffered-crossbar packet switches

Combined input crosspoint buffered (CICB) packet switches were introduced to relax inputoutput arbitration timing and provide high throughput under admissible traffic. However, the amount of memory required in the crossbar of an N x N switch is N2x k x L, where k is the crosspoint buffer size and needs to be of size RTT in cells, L is the packet size. RTT is the round-trip time which is defined by the distance between line cards and switch fabric. When the switch size is large or RTT is not negligible, the memory amount required makes the implementation costly or infeasible for buffered crossbar switches. To reduce the required memory amount, a family of shared memory combined-input crosspoint-buffered (SMCB) packet switches, where the crosspoint buffers are shared among inputs, are introduced in this thesis. One of the proposed switches uses a memory speedup of in and dynamic memory allocation, and the other switch avoids speedup by arbitrating the access of inputs to the crosspoint buffers. These two switches reduce the required memory of the buffered crossbar by 50% or more and achieve equivalent throughput under independent and identical traffic with uniform distributions when using random selections. The proposed mSMCB switch is extended to support differentiated services and long RTT. To support P traffic classes with different priorities, CICB switches have been reported to use N2x k x L x P amount of memory to avoid blocking of high priority cells.The proposed SMCB switch with support for differentiated services requires 1/mP of the memory amount in the buffered crossbar and achieves similar throughput performance to that of a CICB switch with similar priority management, while using no speedup in the shared memory. The throughput performance of SMCB switch with crosspoint buffers shared by inputs (I-SMCB) is studied under multicast traffic. An output-based shared-memory crosspoint buffered (O-SMCB) packet switch is proposed where the crosspoint buffers are shared by two outputs and use no speedup. The proposed O-SMCB switch provides high performance under admissible uniform and nonuniform multicast traffic models while using 50% of the memory used in CICB switches. Furthermore, the O-SMCB switch provides higher throughput than the I-SMCB switch. As SMCB switches can efficiently support an RTT twice as long as that supported by CICB switches and as the performance of SMCB switches is bounded by a matching between inputs and crosspoint buffers, a new family of CICB switches with flexible access to crosspoint buffers are proposed to support longer RTTs than SMCB switches and to provide higher throughput under a wide variety of admissible traffic models. The CICB switches with flexible access allow an input to use any available crosspoint buffer at a given output. The proposed switches reduce the required crosspoint buffer size by a factor of N , keep the service of cells in sequence, and use no speedup. This new class of switches achieve higher throughput performance than CICB switches under a large variety of traffic models, while supporting long RTTs. Crosspoint buffered switches that are implemented in single chips have limited scalability. To support a large number of ports in crosspoint buffered switches, memory-memory-memory (MMM) Clos-network switches are an alternative. The MMM switches that use minimum memory amount at the central module is studied. Although, this switch can provide a moderate throughput, MMM switch may serve cells out of sequence. As keeping cells in sequence in an MMM switch may require buffers be distributed per flow, an MMM with extended memory in the switch modules is studied. To solve the out of sequence problem in MMM switches, a queuing architecture is proposed for an MMM switch. The service of cells in sequence is analyzed

A conflict-free memory banking architecture for fast VOQ packet buffers

In order to support the enormous growth of the Internet, innovative research in every router subsystem is needed. We focus our attention on packet buffer design for routers supporting high-speed line rates. More specifically, we address the design of packet buffers using virtual output queuing (VOQ), which are used in most modern router architectures. The design is based on a previously proposed scheme that uses a combination of SRAM and DRAM modules. We propose a storage scheme that achieves a conflict-free memory bank organization. This leads to a reduction of the granularity of DRAM accesses, resulting in a decrease of storage capacity needed by the SRAM. In the DRAM/SRAM scheme, SRAM memory bandwidth needs to fit the line rate. Since memory bandwidth is limited by its size, searching for memory schemes having a small SRAM size arises as an essential issue for high speed line rates (e.g. OC768, 40 Gbps and OC3072, 160 Gbps).Peer ReviewedPostprint (published version

A low-latency modular switch for CMP systems

[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10% to 21%. Network latency is reduced in a range from 11% to 15%. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04. It was also partly supported by the project NaNoC (Project Label 248972) which is funded by the European Commission within the Research Programme FP7.Roca Pérez, A.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2011). A low-latency modular switch for CMP systems. Microprocessors and Microsystems. 35(8):742-754. https://doi.org/10.1016/j.micpro.2011.08.011S74275435

Scalable design of optical burst switch based on deflection routing.

Deng Yun.Thesis submitted in: July 2003.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 54-56).Abstracts in English and Chinese.Acknowledgments --- p.ii摘要 --- p.iiiAbstract --- p.vChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Optical Switching --- p.1Chapter 1.1.1 --- Optical Circuit Switching --- p.2Chapter 1.1.2 --- Optical Packet Switching --- p.3Chapter 1.1.3 --- Optical Burst Switching --- p.4Chapter 1.2 --- Design of Optical Burst Switching Node --- p.8Chapter 1.2.1 --- Burst Switched Network Architecture --- p.8Chapter 1.2.2 --- Design of Optical Burst Switching Node --- p.10Chapter 1.2.3 --- Scalable Architecture With Multi-plane Fabric --- p.12Chapter 1.3 --- Organization --- p.13Chapter Chapter 2 --- Proposed OBS Node and Blocking probability due to Output Contention --- p.14Chapter 2.1 --- OBS Node Architecture --- p.14Chapter 2.2 --- Burst Traffic Model --- p.16Chapter 2.3 --- Blocking Probability due to Output Contention --- p.17Chapter 2.4 --- Poisson Approximation of Burst Traffic --- p.19Chapter 2.5 --- Simulation Results --- p.21Chapter Chapter 3 --- Deflection Routed Switch Based on Shuffle-exchange network and Burst Loss Rate due to Insufficient Number of Stages --- p.22Chapter 3.1 --- Architecture of Shuffle-exchange Network --- p.22Chapter 3.2 --- The traffic loading entering into the second stage --- p.23Chapter 3.3 --- The Deflection Probability in a 2x2 Switching Module of SN --- p.26Chapter 3.4 --- Analysis of Burst Loss Rate due to Insufficient Number of Stages in SN --- p.27Chapter 3.5 --- Total Burst Loss Probability --- p.30Chapter 3.6 --- Multi-plane Architecture --- p.32Chapter 3.6.1 --- Relationship between k and loading of SN --- p.33Chapter 3.6.2 --- Relationship between k and n: Log2(Number of input-output ports) --- p.36Chapter 3.6.3 --- The result of appropriate number of planes k --- p.38Chapter Chapter 4 --- Switch Based on Dual Shuffle-exchange network and Comparison with Shuffle-exchange network --- p.40Chapter 4.1 --- Architecture of Dual Shuffle-exchange Network --- p.40Chapter 4.2 --- The deflection Probability in a 4x4 Switching Module of DSN --- p.41Chapter 4.3 --- Burst Loss Rate due to Insufficient Number of Stages of DSN --- p.43Chapter 4.4 --- Comparison of SN and DSN --- p.45Chapter 4.4.1 --- Comparison with different n --- p.47Chapter 4.4.2 --- Comparison with different loading --- p.48Chapter 4.4.3 --- The result of comparison --- p.49Chapter Chapter 5 --- Conclusions --- p.50Chapter 5.1 --- The Burst Loss Probability of Proposed OBS Based on SN --- p.51Chapter 5.2 --- The multi-plane Fabric with appropriate number of planes k --- p.51Chapter 5.3 --- Performance of OBS Design Based on DSN and Comparison of SN and DSN --- p.52Bibliography --- p.5