Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

가변기능형 아날로그 블록 기반의 현장 프로그램이 가능한 혼성 신호 집적회로의 설계

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 김재하.Fast-emerging electronic device applications demand a variety of new mixed-signal ICs to be developed in fast cycle and with low cost. While field-programmable gate arrays (FPGAs) are established solutions for timely and low-cost prototyping of digital systems, their counterpart for mixed-signal circuits is still an active area for research. This thesis presents a design of a field-programmable IC for analog/mixed-signal circuits, which solves many challenges with the previous works by performing analog functions in time domain. In order to realize the field-programmable analog functionality, time-domain configurable analog block (TCAB) is proposed. A single TCAB can be programmed to various analog circuits, including a time-to-digital converter, digitally-controlled oscillator, digitally-controlled delay cell, digital pulse-width modulator, and phase interpolator. In addition, the TCABs convey and process analog information using the frequency, pulse width, delay, or phase of digital pulses or pulse sequences, rather than using analog voltage or current signals for less susceptibility to attenuation and noise. This analog information expressed in the digital pulses makes it easy to implement scalable programmable interconnects among the TCABs. The architecture of field-programmable IC capable of emulating todays diverse mixed-signal systems is also introduced. In addition to the TCABs, the proposed IC also includes arrays of configurable logic blocks (CLBs) and programmable arithmetic logic units (ALUs) for programmable digital functions. By programming the functionality of the TCAB, CLB, and ALU arrays and configuring the interconnects, the chip can implement various mixed-signal systems. A prototype IC fabricated with 65-nm CMOS technology demonstrates the versatile programmability of the proposed TCAB and the IC by being successfully operated as a 1-GHz phase-locked loop with a 12.3-psrms integrated jitter, as a 50-MS/s analog-to-digital converter with a 32.5-dB SNDR, and as a 1.2-to-0.7V DC–DC converter with 95.5 % efficiency.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATIONS 1 1.2 THESIS CONTRIBUTION AND ORGANIZATION 5 CHAPTER 2 TIME-DOMAIN CONFIGURABLE ANALOG BLOCK 7 2.1 OVERVIEW OF THE TCAB 9 2.1.1. RECONFIGURABLE FUNCTIONALITY 9 2.1.2. TIME-DOMAIN SIGNAL PROCESSING 14 2.2 CIRCUIT IMPLEMENTATION OF THE TCAB 17 2.3 VERSATILE PROGRAMMABILITY OF TCAB 24 2.3.1. RELAXATION OSCILLATOR 24 2.3.2. DIGITALLY-CONTROLLED OSCILLATOR 28 2.3.3. DIGITAL PULSE-WIDTH MODULATOR 32 2.3.4. GATED OSCILLATOR 34 2.3.5. DIGITALLY-CONTROLLED DELAY CELL 35 2.3.6. PHASE INTERPOLATOR 37 2.3.7. MULTIPHASE DCO 39 2.3.8. NON-OVERLAPPING PULSE GENERATOR 41 2.4 TCAB ARRAY WITH PROGRAMMABLE INTERCONNECTS 43 2.4.1. TCAB ARRAY COMPOSITION 43 2.4.2. PROGRAMMABLE INTERCONNECTS 44 CHAPTER 3 PROPOSED ARCHITECTURE FOR FIELD-PROGRAMMABLE MIXED-SIGNAL IC 49 CHAPTER 4 CIRCUIT IMPLEMENTATION 54 4.1 CONFIGURABLE LOGIC BLOCK ARRAY 55 4.1.1. CONFIGURABLE LOGIC BLOCK 55 4.1.2. CLB ARRAY 56 4.2 ARITHMETIC LOGIC UNIT ARRAY 58 4.2.1. ARITHMETIC LOGIC UNIT 58 4.2.2. ALU ARRAY 61 4.3 INTERFACING BLOCKS 63 4.3.1. VOLTAGE-TO-TIME CONVERTER 64 4.3.2. PHASE-FREQUENCY DETECTOR 65 4.3.3. COUNTER BLOCK 66 4.3.4. TIME-TO-VOLTAGE CONVERTER 68 4.4 PROGRAM METHOD 70 CHAPTER 5 MIXED-SIGNAL EXAMPLES AND EXPERIMENTAL RESULTS 73 5.1 MEASUREMENT RESULTS OF TCAB 76 5.1.1. DIGITAL PULSE-WIDTH MODULATOR 76 5.1.2. DIGITALLY-CONTROLLED OSCILLATOR 79 5.1.3. GATED OSCILLATOR 81 5.2 DIGITAL PHASE-LOCKED LOOP 83 5.3 ANALOG-TO-DIGITAL CONVERTER 89 5.4 DCDC CONVERTER 94 CHAPTER 6 CONCLUSION 99 BIBLIOGRAPHY 101 초 록 108Docto

FIPBLOX: a graphical interactive design tool for FIPSOC

FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI

Built-In Self-Test for Automatic Analog Frequency Response Measurement

Abstract-We present a Built-In Self-Test (BIST) approach based on direct digital synthesizer (DDS) for functional test of analog circuitry in mixed-signal systems. DDS with delta-sigma noise shaping is used to generate test signals with different frequencies and phases. The DDS-based BIST hardware implementation can sweep the frequencies through the interested bands and thus measure the frequency response of the analog circuit. The proposed BIST approach has been implemented in Verilog and synthesized into a Field Programmable Gate Array (FPGA). The actual device under test (DUT) was implemented using a Field Programmable Analog Array (FPAA) to form a complete BIST testbed for analog functional tests

FIPBLOX: a graphical interactive design tool for FIPSOC

FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI

A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

ACE 16k based stand-alone system for real-time pre-processing tasks

This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128×128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.European Commission IST2001 – 38097Ministerio de Ciencia y Tecnología TIC2003 – 09817- C02 – 01Office of Naval Research (USA) N00014021088

Programmable retinal dynamics in a CMOS mixed-signal array processor chip

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5μm CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 × 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.Office of Naval Research (USA) N00014-00-10429European Community IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082