11,937 research outputs found
Redundancy management for efficient fault recovery in NASA's distributed computing system
The management of redundancy in computer systems was studied and guidelines were provided for the development of NASA's fault-tolerant distributed systems. Fault recovery and reconfiguration mechanisms were examined. A theoretical foundation was laid for redundancy management by efficient reconfiguration methods and algorithmic diversity. Algorithms were developed to optimize the resources for embedding of computational graphs of tasks in the system architecture and reconfiguration of these tasks after a failure has occurred. The computational structure represented by a path and the complete binary tree was considered and the mesh and hypercube architectures were targeted for their embeddings. The innovative concept of Hybrid Algorithm Technique was introduced. This new technique provides a mechanism for obtaining fault tolerance while exhibiting improved performance
Pipeline synthetic aperture radar data compression utilizing systolic binary tree-searched architecture for vector quantization
A system for data compression utilizing systolic array architecture for Vector Quantization (VQ) is disclosed for both full-searched and tree-searched. For a tree-searched VQ, the special case of a Binary Tree-Search VQ (BTSVQ) is disclosed with identical Processing Elements (PE) in the array for both a Raw-Codebook VQ (RCVQ) and a Difference-Codebook VQ (DCVQ) algorithm. A fault tolerant system is disclosed which allows a PE that has developed a fault to be bypassed in the array and replaced by a spare at the end of the array, with codebook memory assignment shifted one PE past the faulty PE of the array
On the robustness of bucket brigade quantum RAM
We study the robustness of the bucket brigade quantum random access memory
model introduced by Giovannetti, Lloyd, and Maccone [Phys. Rev. Lett. 100,
160501 (2008)]. Due to a result of Regev and Schiff [ICALP '08 pp. 773], we
show that for a class of error models the error rate per gate in the bucket
brigade quantum memory has to be of order (where is the
size of the memory) whenever the memory is used as an oracle for the quantum
searching problem. We conjecture that this is the case for any realistic error
model that will be encountered in practice, and that for algorithms with
super-polynomially many oracle queries the error rate must be
super-polynomially small, which further motivates the need for quantum error
correction. By contrast, for algorithms such as matrix inversion [Phys. Rev.
Lett. 103, 150502 (2009)] or quantum machine learning [Phys. Rev. Lett. 113,
130503 (2014)] that only require a polynomial number of queries, the error rate
only needs to be polynomially small and quantum error correction may not be
required. We introduce a circuit model for the quantum bucket brigade
architecture and argue that quantum error correction for the circuit causes the
quantum bucket brigade architecture to lose its primary advantage of a small
number of "active" gates, since all components have to be actively error
corrected.Comment: Replaced with the published version. 13 pages, 9 figure
On the Effect of Quantum Interaction Distance on Quantum Addition Circuits
We investigate the theoretical limits of the effect of the quantum
interaction distance on the speed of exact quantum addition circuits. For this
study, we exploit graph embedding for quantum circuit analysis. We study a
logical mapping of qubits and gates of any -depth quantum adder
circuit for two -qubit registers onto a practical architecture, which limits
interaction distance to the nearest neighbors only and supports only one- and
two-qubit logical gates. Unfortunately, on the chosen -dimensional practical
architecture, we prove that the depth lower bound of any exact quantum addition
circuits is no longer , but . This
result, the first application of graph embedding to quantum circuits and
devices, provides a new tool for compiler development, emphasizes the impact of
quantum computer architecture on performance, and acts as a cautionary note
when evaluating the time performance of quantum algorithms.Comment: accepted for ACM Journal on Emerging Technologies in Computing
System
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
The hardware implementation of deep neural networks (DNNs) has recently
received tremendous attention: many applications in fact require high-speed
operations that suit a hardware implementation. However, numerous elements and
complex interconnections are usually required, leading to a large area
occupation and copious power consumption. Stochastic computing has shown
promising results for low-power area-efficient hardware implementations, even
though existing stochastic algorithms require long streams that cause long
latencies. In this paper, we propose an integer form of stochastic computation
and introduce some elementary circuits. We then propose an efficient
implementation of a DNN based on integral stochastic computing. The proposed
architecture has been implemented on a Virtex7 FPGA, resulting in 45% and 62%
average reductions in area and latency compared to the best reported
architecture in literature. We also synthesize the circuits in a 65 nm CMOS
technology and we show that the proposed integral stochastic architecture
results in up to 21% reduction in energy consumption compared to the binary
radix implementation at the same misclassification rate. Due to fault-tolerant
nature of stochastic architectures, we also consider a quasi-synchronous
implementation which yields 33% reduction in energy consumption w.r.t. the
binary radix implementation without any compromise on performance.Comment: 11 pages, 12 figure
Fault Secure Encoder and Decoder for NanoMemory Applications
Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder. We prove that Euclidean geometry low-density parity-check (EG-LDPC) codes have the fault-secure detector capability. Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10^(-18) upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 10^(11) bit/cm^2 with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger EG-LDPC codes can achieve even higher reliability and lower area overhead
High-threshold fault-tolerant quantum computation with analog quantum error correction
To implement fault-tolerant quantum computation with continuous variables,
the Gottesman-Kitaev-Preskill (GKP) qubit has been recognized as an important
technological element. However,it is still challenging to experimentally
generate the GKP qubit with the required squeezing level, 14.8 dB, of the
existing fault-tolerant quantum computation. To reduce this requirement, we
propose a high-threshold fault-tolerant quantum computation with GKP qubits
using topologically protected measurement-based quantum computation with the
surface code. By harnessing analog information contained in the GKP qubits, we
apply analog quantum error correction to the surface code.Furthermore, we
develop a method to prevent the squeezing level from decreasing during the
construction of the large scale cluster states for the topologically protected
measurement based quantum computation. We numerically show that the required
squeezing level can be relaxed to less than 10 dB, which is within the reach of
the current experimental technology. Hence, this work can considerably
alleviate this experimental requirement and take a step closer to the
realization of large scale quantum computation.Comment: 14 pages, 7 figure
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