2,853 research outputs found
๋ฌผ๋ฆฌ์ ์ค๊ณ ์๋ํ์์ ํ์ค์ ํฉ์ฑ ๋ฐ ์ต์ ํ์ ์ค๊ณ ํ์ง ์์ธก ๋ฐฉ๋ฒ๋ก
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2023. 2. ๊นํํ.In the physical design of chip implementation, designing high-quality standard cell layout and accurately predicting post-route DRV (design rule violation) at an early stage is an important problem, especially in advanced technology nodes. This dissertation presents two methodologies that can contribute to improving the design quality and design turnaround time of physical design flow.
Firstly, we propose an integrated approach to the two problems of transistor folding and placement in standard cell layout synthesis. Precisely, we propose a globally optimal algorithm of search tree based design space exploration, devising a set of effective speeding up techniques as well as dynamic programming based fast cost computation. In addition, our algorithm incorporates the minimum oxide diffusion jog constraint, which closely relies on both of transistor folding and placement. Through experiments with the transistor netlists and design rules in advanced node, our proposed method is able to synthesize fully routable cell layouts of minimal size within a very fast time for each netlist, outperforming the cell layout quality in the manual design.
Secondly, we propose a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of pin accessibility and routing congestion on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using advanced node, our model outperforms the existing ML models on all benchmark designs within the fast inference time in comparison with that of the state-of-the-art techniques.์นฉ ๊ตฌํ์ ๋ฌผ๋ฆฌ์ ์ค๊ณ ๋จ๊ณ์์, ๋์ ์ฑ๋ฅ์ ํ์ค ์
์ค๊ณ์ ๋ฐฐ์ ์ฐ๊ฒฐ ์ดํ ์กฐ๊ธฐ์ ์ค๊ณ ๊ท์น ์๋ฐ์ ์ ํํ ์์ธกํ๋ ๊ฒ์ ์ต์ ๊ณต์ ์์ ํนํ ์ค์ํ ๋ฌธ์ ์ด๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ ๋ฌผ๋ฆฌ์ ์ค๊ณ์์์ ์ค๊ณ ํ์ง๊ณผ ์ด ์ค๊ณ ์๊ฐ ํฅ์์ ๋ฌ์ฑํ ์ ์๋ ๋ ๊ฐ์ง ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ๋ค.
๋จผ์ , ๋ณธ ๋
ผ๋ฌธ์์๋ ํ์ค ์
๋ ์ด์์ ํฉ์ฑ์์ ํธ๋์ง์คํฐ ํด๋ฉ๊ณผ ๋ฐฐ์น๋ฅผ ์ข
ํฉ์ ์ผ๋ก ์งํํ ์ ์๋ ๋ฐฉ๋ฒ๋ก ์ ๋
ผํ๋ค. ๊ตฌ์ฒด์ ์ผ๋ก ํ์ ํธ๋ฆฌ ๊ธฐ๋ฐ์ ์ต์ ํ ์๊ณ ๋ฆฌ์ฆ๊ณผ ๋์ ํ๋ก๊ทธ๋๋ฐ ๊ธฐ๋ฐ ๋น ๋ฅธ ๋น์ฉ ๊ณ์ฐ ๋ฐฉ๋ฒ๊ณผ ์ฌ๋ฌ ์๋ ๊ฐ์ ๊ธฐ๋ฒ์ ์ ์ํ๋ค. ์ฌ๊ธฐ์ ๋ํด, ์ต์ ๊ณต์ ์์ ํธ๋์ง์คํฐ ํด๋ฉ๊ณผ ๋ฐฐ์น๋ก ์ธํด ๋ฐ์ํ ์ ์๋ ์ต์ ์ฐํ๋ฌผ ํ์ฐ ์์ญ ์ค๊ณ ๊ท์น์ ๊ณ ๋ คํ์๋ค. ์ต์ ๊ณต์ ์ ๋ํ ํ์ค ์
ํฉ์ฑ ์คํ ๊ฒฐ๊ณผ, ๋ณธ ๋
ผ๋ฌธ์์ ์ ์ํ ๋ฐฉ๋ฒ์ด ์ค๊ณ ์ ๋ฌธ๊ฐ๊ฐ ์๋์ผ๋ก ์ค๊ณํ ๊ฒ ๋๋น ๋์ ์ฑ๋ฅ์ ๋ณด์ด๊ณ , ์ค๊ณ ์๊ฐ๋ ๋งค์ฐ ์งง์์ ๋ณด์ธ๋ค.
๋๋ฒ์งธ๋ก, ๋ณธ ๋
ผ๋ฌธ์์๋ ์
๋ฐฐ์น ๋จ๊ณ์์ ํ ์ ๊ทผ์ฑ๊ณผ ์ฐ๊ฒฐ ํผ์ก์ผ๋ก ์ธํ ์ํฅ์ ์ข
ํฉ์ ์ผ๋ก ๊ณ ๋ คํ ์ ์๋ ๋จธ์ ๋ฌ๋ ๊ธฐ๋ฐ ์ค๊ณ ๊ท์น ์๋ฐ ๊ตฌ์ญ ์์ธก ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ๋ค. ๋จผ์ ํ์ค ์
์ ์
/์ถ๋ ฅ ํ์ ๋ฌผ๋ฆฌ์ ์ ๋ณด์ ํ๊ณผ ํ ์ฌ์ด ๋ฐฉํด ๊ด๊ณ๋ฅผ ํจ๊ณผ์ ์ผ๋ก ํํํ ์ ์๋ ํ ๊ทผ์ ๊ทธ๋ํ๋ฅผ ์ ์ํ๊ณ , ๊ทธ๋ํ ์ ๊ฒฝ๋ง๊ณผ ์ ๋ท ์ ๊ฒฝ๋ง์ ํจ๊ณผ์ ์ผ๋ก ๊ฒฐํฉํ ์๋ก์ด ํํ์ ๋จธ์ ๋ฌ๋ ๋ชจ๋ธ์ ์ ์ํ๋ค. ์ด ๋ชจ๋ธ์์ ๊ทธ๋ํ ์ ๊ฒฝ๋ง์ ํ ๊ทผ์ ๊ทธ๋ํ๋ก๋ถํฐ ํ ์ ๊ทผ์ฑ ์ ๋ณด๋ฅผ ์ถ์ถํ๊ณ , ์ ๋ท ์ ๊ฒฝ๋ง์ ๊ฒฉ์ ๊ธฐ๋ฐ ํน์ง์ผ๋ก๋ถํฐ ์ฐ๊ฒฐ ํผ์ก ์ ๋ณด๋ฅผ ์ถ์ถํ๋ค. ์คํ ๊ฒฐ๊ณผ ๋ณธ ๋
ผ๋ฌธ์์ ์ ์ํ ๋ฐฉ๋ฒ์ ์ด์ ์ฐ๊ตฌ๋ค ๋๋น ๋ ๋น ๋ฅธ ์์ธก ์๊ฐ์ ๋ ๋์ ์์ธก ์ฑ๋ฅ์ ๋ฌ์ฑํจ์ ๋ณด์ธ๋ค.1 Introduction 1
1.1 Standard Cell Layout Synthesis 1
1.2 Machine Learning for Electronic Design Automation 6
1.3 Prediction of Design Rule Violation 8
1.4 Contributions of This Dissertation 11
2 Standard Cell Layout Synthesis of Advanced Nodes with Simultaneous Transistor Folding and Placement 14
2.1 Motivations 14
2.2 Algorithm for Standard Cell Layout Synthesis 16
2.2.1 Problem Definition 16
2.2.2 Overall Flow 18
2.2.3 Step 1: Generation of Folding Shapes 18
2.2.4 Step 2: Search-tree Based Design Space Exploration 20
2.2.5 Speeding up Techniques 23
2.2.6 In-cell Routability Estimation 28
2.2.7 Step 3: In-cell Routing 30
2.2.8 Step 4: Splitting Folding Shapes 35
2.2.9 Step 5: Relaxing Minimum-area Constraints 37
2.3 Experimental Results 38
2.3.1 Comparison with ASAP 7nm Cell Layouts 40
2.3.2 Effectiveness of Dynamic Folding 42
2.3.3 Effectiveness of Speeding Up Techniques 43
2.3.4 Impact of Splitting Folding Shape 48
2.3.5 Runtime Analysis According to Area Relaxation 51
2.3.6 Comparison with Previous Works 52
3 Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction using Graph Neural Network and U-Net 54
3.1 Preliminary 54
3.1.1 Graph Neural Network 54
3.1.2 Fully Convolutional Network 56
3.2 Proposed Prediction Methodology 57
3.2.1 Overall Flow 57
3.2.2 Pin Proximity Graph 58
3.2.3 Grid-based Features 61
3.2.4 Overall Architecture of PGNN 64
3.2.5 GNN Architecture in PGNN 64
3.2.6 U-net Architecture in PGNN 66
3.2.7 Final Prediction in PGNN 66
3.3 Experimental Results 68
3.3.1 Experimental Setup 68
3.3.2 Analysis on PGNN Performance 71
3.3.3 Comparison with Previous Works 72
3.3.4 Adaptation to Real-world Designs 81
3.3.5 Handling Data Imbalance Problem in Regression Model 86
4 Conclusions 92
4.1 Chapter 2 92
4.2 Chapter 3 93๋ฐ
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